Age tracking for independent pipelines
A system and method for efficiently handling instruction execution ordering. In various embodiments, a processor includes multiple execution lanes, each executing instructions of a particular type, which are not executed by one or more of the other execution lanes. The instruction queue includes one queue for each particular execution lane. Control logic identifies a current youngest age used in allocated entries of the multiple queues, and determines a starting age based on the identified current youngest age and the number of instructions to be issued. Beginning with the determined starting age, ages (in program order) are assigned to a group of instructions being allocated in the multiple queues. Ages of entries in the multiple queues are updated for instructions not being issued based on the number of instructions being issued. Instructions being issued have age differences between them below a threshold.
1. An apparatus comprising:
a plurality of queues configured to store instructions to be executed by a plurality of execution lanes; and
circuitry configured to:
identify a first group of instructions comprising a plurality of instructions stored in two or more queues of the plurality of queues that are to be issued to the plurality of execution lanes based at least in part on a determination that the first group of instructions are ready to issue;
determine relative ages of instructions in the first group of instructions to at least two other instructions stored in at least two queues based on an associated count;
identify a second group of instructions of the first group of instructions that have an age difference with one another below a threshold; and
issue the second group of instructions to the plurality of execution lanes, wherein at least two instructions of the second group of instructions are issued to different lanes of the plurality of execution lanes.
2. The apparatus as recited in claim 1 , wherein based at least in part on a determination that one or more instructions of the second group of instructions are assigned to an execution lane capable of flushing its pipeline, the circuitry is further configured to:
generate a vector specifying which lanes of the plurality of execution lanes have assigned instructions of the second group older than an instruction of the second group assigned to the execution lane capable of flushing its pipeline; and
issue the vector with the second group of instructions to the plurality of execution lanes.
3. The apparatus as recited in claim 1 , wherein based at least in part on a determination that a misprediction occurs in a given execution lane of the plurality of execution lanes, the circuitry is further configured to:
determine, for each execution lane other than the given execution lane, whether a given instruction at a same pipeline stage as a mispredicted instruction is older than the mispredicted instruction;
continue execution of the given instruction responsive to determining the given instruction is older than the mispredicted instruction; and
remove the given instruction from the given execution lane responsive to determining the given instruction is younger than the mispredicted instruction.
4. The apparatus as recited in claim 1 , wherein the circuitry is further configured to set the threshold as a number of the plurality of execution lanes less one.
5. The apparatus as recited in claim 1 , wherein the circuitry is further configured to:
identify a current youngest age used in allocated entries of the plurality of queues;
determine a number of instructions in the second group to be issued from the plurality of queues; and
determine a starting age based on the identified current youngest age and the determined number of instructions in the second group to be issued.
6. The apparatus as recited in claim 5 , wherein the circuitry is further configured to:
assign in program order ages to a third group of instructions being allocated in the plurality of queues beginning with the determined starting age; and
allocate the third group of instructions with the assigned ages in the plurality of queues.
7. The apparatus as recited in claim 5 , wherein the circuitry is further configured to update ages of entries in the plurality of queues for instructions not being issued based on the determined number of instructions in the second group to be issued.
8. A method, comprising:
storing, in a plurality of queues by circuitry of an instruction issue queue, instructions to be executed by a plurality of execution lanes;
identifying, by the circuitry, a first group of instructions comprising a plurality of instructions stored in two or more queues of the plurality of queues that are to be issued to the plurality of execution lanes based at least in part on a determination that the first group of instructions are ready to issue;
determining, by the circuitry, relative ages of instructions in the first group of instructions to at least two other instructions stored in at least two queues based on an associated count;
identifying, by the circuitry, a second group of instructions of the first group of instructions that have an age difference with one another below a threshold; and
issuing, by the circuitry, the second group of instructions to the plurality of execution lanes, wherein at least two instructions of the second group of instructions are issued to different lanes of the plurality of execution lanes.
9. The method as recited in claim 8 , wherein in response to determining one or more instructions of the second group of instructions are assigned to an execution lane capable of flushing its pipeline, the method further comprises:
generating a vector specifying which lanes of the plurality of execution lanes have assigned instructions of the second group older than an instruction of the second group assigned to the execution lane capable of flushing its pipeline; and
issuing the vector with the second group of instructions to the plurality of execution lanes.
10. The method as recited in claim 9 , wherein in response to determining a misprediction occurs in a given execution lane of the plurality of execution lanes, the method further comprises:
determining, for each execution lane other than the given execution lane, whether a given instruction at a same pipeline stage as a mispredicted instruction is older than the mispredicted instruction;
continuing execution of the given instruction responsive to determining the given instruction is older than the mispredicted instruction; and
removing the given instruction from the given execution lane responsive to determining the given instruction is younger than the mispredicted instruction.
11. The method as recited in claim 10 , wherein determining whether the given instruction is older than the mispredicted instruction comprises accessing the vector issued with the mispredicted instruction and the given instruction.
12. The method as recited in claim 8 , further comprising:
determining a number of instructions in the second group to be issued from the plurality of queues; and
updating ages of entries in the plurality of queues for instructions not being issued based on the determined number of instructions in the second group to be issued.
13. The method as recited in claim 8 , further comprising setting the threshold as a number of the plurality of execution lanes less one.
14. The method as recited in claim 8 , further comprising:
identifying a current youngest age used in allocated entries of the plurality of queues;
determining a number of instructions in the second group to be issued from the plurality of queues; and
determining a starting age based on the identified current youngest age and the determined number of instructions in the second group to be issued.
15. The method as recited in claim 14 , wherein the method further comprises:
assigning in program order ages to a third group of instructions being allocated in the plurality of queues beginning with the determined starting age; and
allocating the third group of instructions with the assigned ages in the plurality of queues.
16. A processor comprising:
an instruction cache;
a plurality of execution lanes;
an instruction issue queue comprising a plurality of queues configured to store instructions to be executed by the plurality of execution lanes; and
wherein the instruction issue queue is configured to:
store instructions retrieved from the instruction cache;
identify a first group of instructions comprising a plurality of instructions stored in two or more queues of the plurality of queues that are to be issued to the plurality of execution lanes based at least in part on a determination that the first group of instructions are ready to issue;
determine relative ages of instructions in the first group of instructions to at least two other instructions stored in at least two queues based on an associated count;
identify a second group of instructions of the first group of instructions that have an age difference with one another below a threshold; and
issue the second group of instructions to the plurality of execution lanes, wherein at least two instructions of the second group of instructions are issued to different lanes of the plurality of execution lanes.
17. The processor as recited in claim 16 , wherein based at least in part on a determination that one or more instructions of the second group of instructions are assigned to an execution lane capable of flushing its pipeline, the instruction issue queue is further configured to:
generate a vector specifying which lanes of the plurality of execution lanes have assigned instructions of the second group older than an instruction of the second group assigned to the execution lane capable of flushing its pipeline; and
issue the vector with the second group of instructions to the plurality of execution lanes.
18. The processor as recited in claim 16 , wherein based at least in part on a determination that a misprediction occurs in a given execution lane of the plurality of execution lanes, the processor is further configured to:
determine, for each execution lane other than the given execution lane, whether a given instruction at a same pipeline stage as a mispredicted instruction is older than the mispredicted instruction;
continue execution of the given instruction responsive to determining the given instruction is older than the mispredicted instruction; and
remove the given instruction from the given execution lane responsive to determining the given instruction is younger than the mispredicted instruction.
19. The processor as recited in claim 16 , wherein the instruction issue queue is further configured to set the threshold as a number of the plurality of execution lanes less one.
20. The processor as recited in claim 16 , wherein the instruction issue queue is further configured to:
identify a current youngest age used in allocated entries of a plurality of queues;
determine a number of instructions in the second group to be issued from the plurality of queues; and
determine a starting age based on the identified current youngest age and the determined number of instructions in the second group to be issued.