IP Library Granted Patent US 10,636,667
Granted Patent B2
US 10,636,667 · App. 16/121,343 · Granted Apr 28, 2020

Method for manufacturing semiconductor devices and structures thereof

Inventors: Jiann-Horng Lin (Hsinchu, TW); Chao-Kuei Yeh (Changhua County, TW); Ying-Hao Wu (Taoyuan, TW); Tai-Yen Peng (Hsinchu, TW); Chih-Hao Chen (Hsinchu, TW); Chih-Sheng Tian (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L21/3086H01L21/0274H01L21/0332H01L21/0337H01L21/31111H01L21/31144H01L21/76805H01L21/76811
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Quick Facts
Patent No.
US 10,636,667
App. No.
16/121,343
Granted
Apr 28, 2020
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer on the line-end cut pattern; reducing a width of the line-end cut pattern; etching first horizontal portions of the spacer layer with the reduced line-end cut pattern as an etching mask; removing the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the etched line-end cut pattern as an etch mask.

Claims (59)

1. A method of manufacturing a semiconductor device, comprising:

forming a first mandrel and a second mandrel over a mask layer;

depositing a spacer layer over the first mandrel and the second mandrel;

forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel;

depositing a protection layer over the line-end cut pattern;

etching the protection layer;

reducing a width of the line-end cut pattern;

etching first horizontal portions of the spacer layer with the reduced line-end cut pattern as an etching mask;

removing the first mandrel and the second mandrel; and

patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.

2. The method of claim 1 , wherein forming the line-end cut pattern comprises:

forming a patterned mask over the spacer layer, the patterned mask comprising an opening exposing a portion of the spacer layer between the first mandrel and the second mandrel;

depositing a sacrificial material in the opening; and

removing excess portions of the sacrificial material over the opening using a planarization operation.

3. The method of claim 1 , wherein the etching of the protection layer is performed by a same operation as that reducing the width of the line-end cut pattern.

4. The method of claim 1 , wherein reducing a width of the line-end cut pattern also reduces a height of the line-end cut pattern.

5. The method of claim 1 , wherein depositing a protection layer over the line-end cut pattern comprises depositing the protection layer to cover an upper surface and sidewalls of the spacer layer.

6. The method of claim 1 , wherein etching the protection layer on the line-end cut pattern comprises etching sidewalls of the protection layer at a first etch rate greater than a second etch rate on horizontal portions of the protection layer.

7. The method of claim 1 , wherein the protection layer comprises at least one of a nitride, an oxide and a carbon-based material.

8. The method of claim 1 , wherein the line-end cut pattern comprises titanium oxide, tantalum oxide, silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

9. The method of claim 1 , wherein the line-end cut pattern comprises at least one pillar, further comprising patterning a target layer using the patterned mask layer and forming segments of a conductive line in the target layer, wherein a width of the pillar corresponds to a spacing of the segments.

10. The method of claim 1 , wherein the line-end cut pattern masks a second horizontal portion of the spacer layer while removing the first horizontal portions of the spacer layer.

11. A method of manufacturing a semiconductor device, comprising:

patterning a first opening in a mandrel layer;

depositing a spacer layer over and along sidewalls of the first opening;

forming a first patterned mask over the spacer layer, wherein the first patterned mask comprises a second opening exposing a portion of the spacer layer on a bottom portion of the first opening;

depositing a sacrificial material in the second opening;

removing the first patterned mask;

forming a line-end cut pattern by etching the sacrificial material;

depositing a protection layer covering the line-end cut pattern;

trimming the line-end cut pattern and the protection layer;

patterning the spacer layer so that portions of the spacer layer remain on sidewalls of the mandrel layer; and

forming a second patterned mask by removing the mandrel layer while leaving the trimmed line-end cut pattern and the patterned spacer layer.

12. The method of claim 11 , wherein the sacrificial material is differentiated from the spacer layer by an etching selectivity of between about 3 and about 10.

13. The method of claim 11 , wherein the protection layer is differentiated from the spacer layer by an etching selectivity of between about 3 and about 10.

14. The method of claim 11 , wherein the sacrificial material is an inorganic material.

15. The method of claim 11 , wherein the line-end cut pattern masks a bottom portion of the spacer layer in the first opening from being etched while the spacer layer is patterned.

16. The method of claim 11 , wherein forming a first patterned mask over the spacer layer comprises:

depositing a photoresist stack over the spacer layer; and

forming the second opening through the photoresist stack.

17. The method of claim 16 , wherein depositing a photoresist stack over the spacer layer comprises:

depositing a bottom layer over the spacer layer;

depositing a middle layer over the bottom layer;

depositing an upper layer over the middle layer; and

prior to depositing the sacrificial material in the second opening, removing the upper layer.

18. A method comprising:

patterning a plurality of mandrels over a mask layer;

depositing a spacer layer over and along sidewalls of the plurality of mandrels;

forming a patterned mask over the spacer layer, the patterned mask comprising an opening exposing a portion of the spacer layer between adjacent ones of the plurality of mandrels;

depositing a sacrificial material over the patterned mask in the opening;

removing the patterned mask thereby forming a line-end cut pattern on the spacer layer;

depositing a protection layer covering the sacrificial material and the spacer layer;

trimming the protection layer while leaving the spacer layer covered by the protection layer;

reducing a width of the line-end cut pattern;

patterning the spacer layer to expose the plurality of mandrels;

removing the plurality of mandrels; and

patterning the mask layer using sidewall portions of the spacer layer and the reduced line-end cut pattern as an etch mask.

19. The method of claim 18 , further comprising completely removing the protection layer prior to patterning the spacer layer.

20. The method of claim 18 , wherein depositing the sacrificial material comprises depositing the sacrificial material at about 200° C. or below.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2018
From: LIN, JIANN-HORNG; YEH, CHAO-KUEI; WU, YING-HAO; PENG, TAI-YEN; CHEN, CHIH-HAO; TIAN, CHIH-SHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 047020/0443 →
Continuity (2)
Provisional Application 62589162 · Nov 21, 2017
Related Publication 20190157094A1 · May 23, 2019