Transistorless memory cell

1. An integrated chip, comprising:

an operative magnetic tunnel junction (MTJ) device with an operative free layer directly coupled to a bit-line, wherein the operative MTJ device is configured to store a data state;

a regulating access apparatus coupled between the operative MTJ device and a first word-line, wherein the regulating access apparatus comprises one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device;

wherein the operative MTJ device comprises an operative pinned layer; and

wherein the one or more regulating MTJ devices comprise a regulating free layer directly coupled to the operative pinned layer.

2. The integrated chip of claim 1 , wherein the regulating access apparatus comprises:

a first regulating MTJ device coupled between the first word-line and the operative MTJ device; and

a second regulating MTJ device coupled between a second word-line and the operative MTJ device, wherein the first word-line and the second word-line are coupled to a word-line decoder.

3. The integrated chip of claim 2 , wherein the operative MTJ device consist of a first terminal and a second terminal.

4. The integrated chip of claim 1 , wherein the regulating access apparatus comprises:

a first regulating MTJ device coupled between the first word-line and the operative MTJ device; and

a second regulating MTJ device coupled between a second bit-line and the operative MTJ device, wherein the first word-line is coupled to a word-line decoder and the bit-line and the second bit-line are coupled to a bit-line decoder.

5. The integrated chip of claim 1 , further comprising:

a bias-voltage-line coupled between a first regulating MTJ device and the operative MTJ device.

6. The integrated chip of claim 1 , wherein the operative MTJ device is laterally separated from a first regulating MTJ device by a dielectric structure disposed over a substrate.

7. The integrated chip of claim 6 , further comprising:

a second operative MTJ device arranged within a memory cell that is directly over the operative MTJ device, wherein the second operative MTJ device is configured to store a second data state.

8. The integrated chip of claim 1 , wherein the operative MTJ device is coupled between the bit-line and the first word-line by way of a continuous conductive path that does not extend through a semiconductor substrate underlying the operative MTJ device.

9. The integrated chip of claim 1 , wherein the regulating access apparatus comprises:

a regulating pinned layer coupled to the first word-line and seperated from the regulating free layer by a regulating tunnel dielectric layer.

10. An integrated circuit, comprising:

a first interconnect arranged within a dielectric structure over a substrate and defining a first word-line, wherein the first interconnect is separated from the substrate by the dielectric structure;

an operative magnetic tunnel junction (MTJ) device with an operative pinned layer arranged over the first interconnect and configured to store a data state;

a second interconnect arranged within the dielectric structure over the operative MTJ device and defining a first bit-line; and

a first regulating MTJ device with a regulating free layer directly wired to the operative pinned layer.

11. The integrated circuit of claim 10 , wherein the first interconnect continuously extends from directly below the operative MTJ device to directly below the first regulating MTJ device.

12. The integrated circuit of claim 10 , further comprising:

a third interconnect arranged within the dielectric structure and defining a second word-line; and

a second regulating MTJ device coupled between the third interconnect and the operative MTJ device, wherein the first interconnect and the third interconnect are coupled to a word-line decoder.

13. The integrated circuit of claim 12 , wherein the first regulating MTJ device has a different size than the second regulating MTJ device.

14. The integrated circuit of claim 12 , further comprising:

a bias-voltage-line coupled between the operative MTJ device and the first regulating MTJ device and the second regulating MTJ device, wherein the bias-voltage-line is coupled to a bias circuit configured to selectively apply a bias voltage to the bias-voltage-line.

15. The integrated circuit of claim 10 , further comprising:

a fourth interconnect arranged within the dielectric structure and defining a second bit-line; and

a second regulating MTJ device coupled between the fourth interconnect and the operative MTJ device, wherein the first interconnect is coupled to a word-line decoder and the fourth interconnect is coupled to a bit-line decoder.

16. The integrated circuit of claim 10 , further comprising:

a bias-voltage-line coupled between the first regulating MTJ device and the operative MTJ device, wherein the bias-voltage-line is coupled to a bias circuit configured to selectively apply a bias voltage to the bias-voltage-line.

17. The integrated circuit of claim 10 , wherein the first word-line is coupled to a pinned layer of the first regulating MTJ device, and a free layer of the operative MTJ device is coupled to the first bit-line.

18. A method of forming an integrated circuit, comprising:

forming a first interconnect layer over a substrate;

forming a plurality of MTJ devices directly over the first interconnect layer, wherein the plurality of MTJ devices comprise an operative MTJ device and a regulating MTJ device, and wherein the operative MTJ device consists of a first terminal and a second terminal and the regulating MTJ device consists of a third terminal and a fourth terminal, the first terminal, the second terminal, the third terminal, and the fourth terminal being different terminals; and

forming a second interconnect layer over the plurality of MTJ devices, wherein one or both of the first interconnect layer and the second interconnect layer define a bit-line and one or more word-lines.

19. The method of claim 18 ,

wherein the operative MTJ device comprises an operative pinned layer; and

wherein the regulating MTJ device comprises a regulating free layer directly coupled to the operative pinned layer.

20. The method of claim 18 , wherein the operative MTJ device and the regulating MTJ device are concurrently formed.