Semiconductor integrated circuit including a memory macro
View Patent ↗In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.
1. A semiconductor integrated circuit comprising a memory macro including:
a first error correction code (ECC) circuit that generates an error detection and correction code corresponding to input data;
a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed;
a second ECC circuit that performs error detection or correction of data to be read from the data storage portion, using a code to be read from the ECC storage portion;
a first path in which data flows from the first ECC circuit through each of the data storage portion and the ECC storage portion to the second ECC circuit in a memory test; and
a second path in which data flows, from the first ECC circuit to the second ECC circuit, to bypass the memory core in a scan test.
2. The semiconductor integrated circuit according to claim 1 , further comprising:
a first latch circuit provided on an input side of the data storage portion, and a second latch circuit provided on an output side of the data storage portion; and
a third latch circuit provided on an input side of the ECC storage portion, and a fourth latch circuit provided on an output side of the ECC storage portion,
wherein:
the first latch circuit and the second latch circuit are configured to operate as a flip-flop together in the scan test, and
the third latch circuit and the fourth latch circuit are configured to operate as a flip-flop together in the scan test.
3. The semiconductor integrated circuit according to claim 1 , wherein
the memory macro further includes a first selector that selects a path in the memory test such that part of the data output from a data output terminal of the first ECC circuit flows to the ECC storage portion.
4. The semiconductor integrated circuit according to claim 3 , wherein
the first selector is achieved using a multiplexer.
5. The semiconductor integrated circuit according to claim 1 , wherein
the memory macro further includes a second selector that selects a path in the memory test such that one of a path in which data output from the data storage portion flows to a data input terminal of the second ECC circuit and a path in which data output from the ECC storage portion flows to the data input terminal of the second ECC circuit is made effective.
6. The semiconductor integrated circuit according to claim 5 , further comprising: a memory test circuit that execute, in the memory test, a test for each of the data storage portion and the ECC storage portion, by supplying test data into the memory macro while operating the second selector.
7. The semiconductor integrated circuit according to claim 6 , wherein the memory test circuit is a built-in self-test (BIST) circuit included in the semiconductor integrated circuit.
8. The semiconductor integrated circuit according to claim 5 , wherein
the second selector is achieved using a multiplexer.
9. The semiconductor integrated circuit according to claim 1 , further comprising: an input that receives a signal that sets, in the memory test, processing functions of the first and the second ECC circuits to disabled states such that data input to each of the first and the second ECC circuits are output without any processing.
10. The semiconductor integrated circuit according to claim 1 , wherein
the memory core is a static random access memory (SRAM) core.
11. The semiconductor integrated circuit according to claim 1 , wherein
the memory macro is a SRAM macro.