Electronic device including high electron mobility transistors

1. An electronic device comprising:

a first high electron mobility transistor including:

a drain electrode overlying a channel layer;

a first gate electrode overlying the channel layer; and

a second high electron mobility transistor including:

a drain coupled to a source of the first high electron mobility transistor;

a source electrode overlying a channel layer; and

a second gate electrode electrically connected to the source electrode.

2. The electronic device of claim 1 , wherein the first and second high electron mobility transistors have different threshold voltages.

3. The electronic device of claim 1 , wherein the second high electron mobility transistor includes a Schottky-gated high electron mobility transistor.

4. The electronic device of claim 1 , wherein the first high electron mobility transistor is an enhancement-mode transistor, and the second high electron mobility transistor is a depletion-mode transistor.

5. The electronic device of claim 1 , wherein the second high mobility electron transistor further comprises a dielectric layer disposed between the second gate electrode and the channel layer.

6. The electronic device of claim 5 , wherein the dielectric layer has a relative permittivity and a thickness, wherein a ratio of the relativity permittivity divided by the thickness is at least 0.62 nm −1 .

7. The electronic device of claim 6 , wherein the ratio of the relative permittivity divided by the thickness is at most 3.9 nm −1 .

8. The electronic device of claim 5 , wherein the dielectric layer comprises Si 3 N 4 , Al 2 O 3 , ZrO 2 , HfO 2 , SiO 2 , TiO 2 , Ta 2 O 5 , or Nb 2 O 3 .

9. The electronic device of claim 1 , wherein a threshold voltage of the second high electron mobility transistor is in a range from −1 V to −4 V.

10. The electronic device of claim 1 , wherein the second high electron mobility transistor is configured to limit current to at most 0.4 A/mm.

11. The electronic device of claim 1 , wherein:

the first high electron mobility transistor is an enhancement-mode transistor,

the second high electron mobility transistor is a Schottky-gated transistor or a depletion-mode transistor.

12. The electronic device of claim 11 , wherein a threshold voltage of the second high electron mobility transistor is in a range from −1 V to −4 V, and the second high electron mobility transistor is configured to limit current to at most 0.4 A/mm.

13. A process of forming an electronic device comprising:

forming a first gate electrode of a first high electron mobility transistor;

forming a drain electrode of the first high electron mobility transistor over a channel layer;

forming a source electrode of a second high electron mobility transistor, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and

forming a gate electrode of a second high electron mobility transistor, wherein:

the gate electrode of the second high electron mobility transistor is electrically connected to the source electrode of the second high electron mobility transistor, and

a source of the first high electron mobility transistor is coupled to a drain of the second high electron mobility transistor.

14. The process of claim 13 , wherein:

forming the source electrode comprises forming the source electrode such that it forms an ohmic contact with the channel layer or a barrier layer overlying the channel layer;

forming the drain electrode comprises forming the drain electrode such that it forms an ohmic contact with the barrier layer or the channel layer; and

forming the gate electrode of the second high electron mobility transistor comprises forming a Schottky contact between a metal-containing layer and the barrier layer or the channel layer.

15. The process of claim 13 , wherein forming the second high electron mobility transistor comprises forming a dielectric layer before forming the second gate electrode, wherein the dielectric layer is part of the second high electron mobility transistor.

16. The process of claim 13 , wherein forming the first gate electrode comprises forming a p-type semiconductor layer over a first gate region of the first high electron mobility transistor.

17. The process of claim 13 , further comprising:

forming an interlevel dielectric layer; and

patterning the interlevel dielectric layer to define contact openings for the source electrode of the second high electron mobility transistor and the gate electron of the second high electron mobility transistor,

wherein forming the source electrode of the source electrode of the second high electron mobility transistor and forming the gate electron of the second high electron mobility transistor comprises:

depositing a conductive layer over the interlevel dielectric layer and within the contact openings; and

patterning to the conductive layer to form an interconnect that includes:

a source electrode portion corresponding to the source electrode of the second high electron mobility transistor; and

a gate electrode portion corresponding to the gate electrode of the second high electron mobility transistor and a gate portion.

18. A circuit comprising:

a drain terminal;

a source terminal;

a gate terminal;

a first high electron mobility transistor including a drain, a source, and a gate, wherein:

the drain of the first high electron mobility transistor is coupled to the drain terminal, and

the gate of the first high electron mobility transistor is coupled to the gate terminal; and

a second high electron mobility transistor including a drain, a source, and a gate, wherein:

the drain of the second high electron mobility transistor is coupled to the source of the first high electron mobility transistor,

the source of the second high electron mobility transistor is electrically connected to the gate of the second high electron mobility transistor,

the source and gate of the second high electron mobility transistor arc coupled to the source terminal, and

the second high electron mobility transistor is a Schottky-gated high electron mobility transistor.

19. The circuit of claim 18 , wherein the second high electron mobility transistor includes a Schottky-gated high electron mobility transistor.

20. The circuit of claim 18 , wherein the second high electron mobility transistor is configured to limit current to at most 0.4 A/mm.