IP Library Granted Patent US 11,132,037
Granted Patent B2
US 11,132,037 · App. 16/123,189 · Granted Sep 28, 2021

Operating temperature management of a memory sub-system

Inventors: Shane Nowell (Boise, ID); Sivagnanam Parthasarathy (Carlsbad, CA)
Assignee: Micron Technology, Inc.
G06F1/206G01K3/005G06F1/203G11C11/5635
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Quick Facts
Patent No.
US 11,132,037
App. No.
16/123,189
Granted
Sep 28, 2021
Kind
B2
Abstract

An operating temperature of a memory sub-system is identified. It is determined that the identified operating temperature satisfies a first temperature condition. Upon determining that the identified operating temperature satisfies the first temperature condition, operations are performed at the memory sub-system until the operating temperature changes to satisfy a second temperature condition.

Claims (51)

1. A system comprising:

a memory component of a memory sub-system; and

a processing device, operatively coupled with the memory component, to:

identify an operating temperature of the memory sub-system;

determine that the operating temperature satisfies a first temperature condition outside of a temperature range defined by a first threshold temperature and a second threshold temperature; and

upon determining that the operating temperature satisfies the first temperature condition, perform one or more operations at the memory sub-system until the operating temperature changes to satisfy a second temperature condition within the temperature range.

2. The system of claim 1 , wherein to determine that the operating temperature satisfies the first temperature condition, the processing device is to:

determine that the operating temperature is below the first threshold temperature, and wherein the operating temperature satisfies the second temperature condition when the operating temperature changes to be equal to or above the first threshold temperature.

3. The system of claim 1 , wherein to perform the one or more operations at the memory sub-system, the processing device is to:

perform the one or more operations on a data block at the memory component of the memory sub-system.

4. The system of claim 3 , wherein to perform the one or more operations on the data block at the memory component, the processing device is to perform one or more of:

a read operation associated with the data block at the memory component;

a write operation associated with the data block at the memory component; or

an erase operation associated with the data block at the memory component.

5. The system of claim 1 , wherein to perform the one or more operations at the memory sub-system, the processing device is to:

perform an operation associated with a temperature control element that is proximate to the memory component of the memory sub-system.

6. The system of claim 1 , wherein to determine that the operating temperature satisfies the first temperature condition, the processing device is to determine that the operating temperature is above the second threshold temperature, and wherein to perform the one or more operations at the memory sub-system until the operating temperature satisfies the second temperature condition, the processing device is to:

perform the one or more operations until the operating temperature is equal to or below the second threshold temperature.

7. The system of claim 2 , wherein the one or more operations are performed based on a difference between the operating temperature and the first threshold temperature.

8. The system of claim 1 , further comprising:

a temperature sensor to detect the operating temperature of the memory sub-system.

9. The system of claim 1 , further comprising:

a temperature comparator to perform a temperature comparison operation between two or more temperature values to determine whether the operating temperature satisfies the first temperature condition.

10. A method comprising:

identifying an operating temperature of a memory sub-system;

determining that the operating temperature satisfies a first temperature condition outside of a temperature range defined by a first threshold temperature and a second threshold temperature; and

upon determining that the identified operating temperature satisfies the first temperature condition, performing, by a processing device, one or more operations at the memory sub-system until the operating temperature changes to satisfy a second temperature condition within the temperature range.

11. The method of claim 10 , wherein determining that the identified operating temperature satisfies the first temperature condition comprises:

determining that the operating temperature is below the first threshold temperature, and wherein the operating temperature satisfies the second temperature condition when the operating temperature changes to be equal to or above the first threshold temperature.

12. The method of claim 10 , wherein performing one or more operations at the memory sub-system comprises:

performing the one or more operations on a data block at a memory component of the memory sub-system.

13. The method of claim 12 , wherein performing the one or more operations on the data block at the memory component comprises performing one or more of:

a read operation associated with the data block at the memory component;

a write operation associated with the data block at the memory component; or

an erase operation associated with the data block at the memory component.

14. The method of claim 10 , wherein performing the one or more operations at the memory sub-system comprises:

performing an operation associated with a temperature control element that is proximate to a memory component of the memory sub-system.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

identify an operating temperature of a memory sub-system;

determine that the operating temperature of the memory sub-system is outside of a temperature range associated with the memory sub-system; and

in response to determining that the operating temperature of the memory sub-system is outside of the temperature range, activate a temperature control element to change the operating temperature of the memory sub-system to be within the temperature range.

16. The non-transitory computer-readable storage medium of claim 15 , wherein to activate the temperature control element, the processing device is to:

perform an operation associated with the temperature control element that is proximate to the memory component of the memory sub-system.

17. The non-transitory computer-readable storage medium of claim 15 , wherein to determine that the operating temperature of the memory sub-system is outside of the temperature range associated with the memory sub-system, the processing device is to:

determine that the operating temperature is below a first threshold temperature.

18. The non-transitory computer-readable storage medium of claim 17 , wherein to activate the temperature control element, the processing device is to:

perform an operation associated with the temperature control element until the operating temperature of the memory sub-system is equal to or above the first threshold temperature.

19. The non-transitory computer-readable storage medium of claim 15 , wherein to determine that the operating temperature of the memory sub-system is outside of the temperature range associated with the memory sub-system, the processing device is to:

determine that the operating temperature is above a second threshold temperature.

20. The non-transitory computer-readable storage medium of claim 19 , wherein to activate the temperature control element, the processing device is to:

perform an operation associated with the temperature control element until the operating temperature of the memory sub-system is equal to or below the second threshold temperature.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 065514/0068 →
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2018
From: NOWELL, SHANE; PARTHASARATHY, SIVAGNANAM
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046829/0649 →
Continuity (1)
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