Microelectronic devices, electronic systems, and related methods

1. A microelectronic device, comprising:

a stack comprising an alternating sequence of dielectric structures and conductive structures;

a channel structure vertically extending through the stack and comprising a first semiconductor material having a first band gap;

a conductive plug structure in direct physical contact with the channel structure, upper surfaces of the channel structure and the conductive plug structure are coplanar with one another;

a band offset structure in direct physical contact with the channel structure and the conductive plug structure, the band offset structure comprising a second semiconductor material having a second band gap different than the first band gap; and

a conductive line structure in direct physical contact with the conductive plug structure.

2. The microelectronic device of claim 1 , wherein the conductive plug structure comprises a conductive material having a third band gap, the second band gap being smaller than each of the first band gap and the third band gap.

3. The microelectronic device of claim 2 , wherein the third band gap is substantially equal to the first band gap.

4. The microelectronic device of claim 1 , wherein:

an interface between the band offset structure and the channel structure comprises a heterojunction; and

another interface between the conductive plug structure and the channel structure comprises a homojunction.

5. The microelectronic device of claim 1 , wherein the conductive line structure comprises a data line, and the band offset structure is remote from the data line.

6. The microelectronic device of claim 1 , wherein the band offset structure directly physical contacts the channel structure along a single vertical interface.

7. The microelectronic device of claim 1 , wherein the stack comprising the alternating sequence of dielectric structures and conductive structures comprises alternating regions of an insulating material and a conductive material arranged in stacked tiers overlying a base material, each of the stacked tiers comprising one of the dielectric structures and one of the conductive structures.

8. The microelectronic device of claim 1 , wherein the band offset structure is in direct physical contact with an internal sidewall of the channel structure.

9. The microelectronic device of claim 1 , wherein a vertical interface between the conductive plug structure and the channel structure is configured to provide an electrical pathway therethrough, and another vertical interface between the band offset structure and the channel structure is configured to impede an electrical pathway therethrough.

10. A microelectronic device, comprising:

a stack comprising an alternating sequence of dielectric structures and conductive structures;

a channel structure vertically extending through the stack, the channel structure comprising a first semiconductor material including an n-type dopant and having a first band gap;

a conductive plug structure in direct physical contact with the channel structure and comprising the n-type dopant, the conductive plug structure having a greater concentration of the n-type dopant than the channel structure;

a band offset structure in direct physical contact with the channel structure and the conductive plug structure, the band offset structure comprising a second semiconductor material including a p-type dopant and having a second band gap different than the first band gap; and

a conductive line structure electrically coupled to the conductive plug structure.

11. A method of forming a microelectronic device, comprising:

forming an opening vertically extending through a stack of alternating conductive gate materials and dielectric materials;

forming a channel material comprising a first semiconductor material having a first band gap within the opening;

forming a band offset material comprising a second semiconductor material having a second band gap within the opening and in direct physical contact with the channel material;

forming a conductive plug material within the opening and in direct physical contact with the channel material and the band offset material with an upper surface of the conductive plug material coplanar with an upper surface of the channel material, the second band gap of the band offset material different than each of the first band gap of the channel material and a third band gap of the conductive plug material; and

forming a conductive line structure in direct physical contact with the conductive plug material.

12. The method of claim 11 , wherein

forming the band offset material comprises:

forming the band offset material within the opening and in direct physical contact with an internal sidewall of the channel material; and

electrically coupling the band offset material to the channel material without electrically coupling the band offset material to the conductive line structure.

13. The method of claim 11 , wherein forming the channel material within the opening comprises conformally forming the channel material on internal sidewalls of a cylindrical-shaped opening.

14. The method of claim 11 , wherein forming the band offset material comprises:

conformally forming the band offset material along an exposed upper surface of a central dielectric material, along an internal sidewall of the channel material, and over an upper surface of the stack; and

removing portions of the band offset material along the exposed upper surface of the central dielectric material and over the upper surface of the stack.

15. The method of claim 11 , wherein forming the band offset material comprises epitaxially growing the band offset material within the opening.

16. The method of claim 11 , wherein forming the band offset material comprises selecting the second band gap of the band offset material to be smaller than each of the third band gap of the conductive plug material and the first band gap of the channel material.

17. The method of claim 11 , wherein forming the opening vertically extending through the stack of alternating conductive gate materials and dielectric materials comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a base material prior to forming the opening.

18. An electronic system including a microelectronic device, comprising:

a processor; and

a microelectronic device electrically coupled to the processor, the microelectronic device comprising:

vertical structures vertically extending through a stack of vertically alternating conductive materials and dielectric materials, each of the vertical structures comprising:

a channel material;

plug material adjacent the channel material, the plug material comprising:

a lower portion comprising a bottom surface in direct physical contact with a central dielectric material; and

an upper portion having a greater radial extent than the lower portion and comprising a side surface of the upper portion in direct physical contact with the channel material; and

band offset material in direct contact with each of the channel material and the plug material, the band offset material comprising a radially extending portion laterally surrounding the lower portion of the plug material, and a band gap of the band offset material different from that of each of the channel material and the plug material;

data lines above the vertical structures; and

an uppermost conductive gate material laterally adjacent the vertical structures, the plug material at least partially vertically overlapping the uppermost conductive gate material.

19. The electronic system of claim 18 , wherein the plug material comprises a polycrystalline silicon material, and wherein the band offset material is selected from the group consisting of silicon germanium, germanium, and indium gallium arsenide.

20. The electronic system of claim 18 , wherein the data lines are in direct physical contact with the plug material without being in direct physical contact with the band offset material.