Semiconductor memory device
A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.
1. A semiconductor memory device comprising:
a bit line;
a channel pattern including a horizontal channel portion on the bit line; and a vertical channel portion vertically protruding from the horizontal channel portion;
a word line on the horizontal channel portion and on a sidewall of the vertical channel portion; and
a gate insulating pattern between the word line and the channel pattern,
wherein the channel pattern includes an oxide semiconductor and comprises first, second, and third channel layers stacked sequentially,
the first to third channel layers include a first metal,
the second channel layer further includes a second metal different from the first metal, and
at least a portion of the first channel layer contacts the bit line.
2. The semiconductor memory device of claim 1 , wherein the third channel layer contacts the gate insulating pattern.
3. The semiconductor memory device of claim 1 , wherein
a thickness of the first channel layer is equal to a thickness of the third channel layer, and
a thickness of the second channel layer is greater than the thickness of the first or third channel layer.
4. The semiconductor memory device of claim 1 , wherein
the first metal includes gallium (Ga), and
the second metal includes indium (In).
5. The semiconductor memory device of claim 1 , wherein a composition ratio of the first metal in each of the first and third channel layers is greater than a composition ratio of the first metal in the second channel layer.
6. The semiconductor memory device of claim 1 , wherein
the word line includes a horizontal portion on the horizontal channel portion of the channel pattern, and a vertical portion on the sidewall of the vertical channel portion of the channel pattern, and
the horizontal portion is aligned with an inner sidewall of the vertical channel portion.
7. The semiconductor memory device of claim 6 , further comprising:
a spacer on the horizontal portion of the word line,
wherein the spacer is aligned with a sidewall of the horizontal portion of the word line.
8. The semiconductor memory device of claim 1 , wherein
the horizontal channel portion of the channel pattern has a first thickness on the bit line,
the vertical channel portion of the channel pattern has a second thickness on an outer sidewall of the word line, and
the first thickness and the second thickness are equal to each other.
9. The semiconductor memory device of claim 1 , wherein a top surface of the word line is at a lower level than a top surface of the vertical channel portion of the channel pattern.
10. The semiconductor memory device of claim 1 , further comprising:
a data storage pattern electrically connected to the vertical channel portion of the channel pattern; and
a landing pad between the vertical channel portion of the channel pattern and the data storage pattern,
wherein the first to third channel layers contact the landing pad.
11. A semiconductor memory device comprising:
a bit line;
a channel pattern including a horizontal channel portion on the bit line and first and second vertical channel portions vertically protruding from the horizontal channel portion and facing each other;
first and second word lines on the horizontal channel portion and between the first and second vertical channel portions;
a gate insulating pattern between the channel pattern and the first and second word lines; and
an insulating pattern between the first and second word lines,
wherein the channel pattern includes an oxide semiconductor and comprises first, second, and third channel layers sequentially stacked,
the first to third channel layers include a first metal,
the second channel layer further includes a second metal different from the first metal, and
at least a portion of the first channel layer contacts the bit line.
12. The semiconductor memory device of claim 11 , wherein the third channel layer contacts the gate insulating pattern.
13. The semiconductor memory device of claim 11 , wherein
a thickness of the first channel layer is equal to a thickness of the third channel layer, and
a thickness of the second channel layer is greater than the thickness of the first or third channel layer.
14. The semiconductor memory device of claim 11 , wherein
the first metal includes gallium (Ga),
the second metal includes indium (In), and
a composition ratio of the first metal in each of the first and third channel layers is greater than a composition ratio of the first metal in the second channel layer.
15. The semiconductor memory device of claim 11 , wherein the first and second word lines include first and second horizontal portions on the horizontal channel portions of the channel pattern, and first and second vertical portions located on sidewalls of the first and second vertical channel portions of the channel pattern, respectively, and
the first horizontal portion is aligned with an inner sidewall of the first vertical channel portion, and the second horizontal portion is aligned with an inner sidewall of the second vertical channel portion.
16. The semiconductor memory device of claim 15 , further comprising:
a first spacer on the first horizontal portion of the first word line; and
a second spacer on the second horizontal portion of the second word line,
wherein the first and second spacers are aligned with the sidewalls of the first and second horizontal portions of the first and second word lines, respectively.
17. The semiconductor memory device of claim 11 , wherein
the gate insulating pattern comprises a first gate insulating pattern between the first word line and the channel pattern, and a second gate insulating pattern between the second word line and the channel pattern, and
the insulating pattern contacts a portion of the horizontal channel portion of the channel pattern.
18. The semiconductor memory device of claim 11 , wherein
the channel pattern comprises a first channel pattern including a first horizontal channel portion and the first vertical channel portion, and a second channel pattern including a second horizontal channel portion and the second vertical channel portion, and
wherein the insulating pattern is in contact with a portion of the bit line.
19. A semiconductor memory device comprising:
a peripheral circuit structure comprising peripheral circuits on a semiconductor substrate, the peripheral circuit structure further comprising a lower insulating layer covering the peripheral circuits;
bit lines extending in a first direction on the peripheral circuit structure;
a first insulating pattern defining a trench extending in a second direction, the trench intersecting the bit lines;
channel patterns spaced apart from each other in the second direction in the trench, wherein each of the channel patterns includes first and second vertical channel portions facing each other, and a horizontal channel portion connecting the first and second vertical channel portions;
first and second word lines extending in the second direction on the horizontal channel portions of the channel patterns, the first word lines adjacent to the first vertical channel portions of the channel patterns, and the second word lines adjacent to the second vertical channel portions of the channel patterns;
a gate insulating pattern between the channel patterns and the first and second word lines and extending in the second direction;
a second insulating pattern covering the first and second word lines in the trench;
first data storage patterns on the first vertical channel portions of the channel patterns; and
second data storage patterns on the second vertical channel portions of the channel patterns,
wherein each of the channel patterns includes an oxide semiconductor and comprises first, second, and third channel layers stacked sequentially,
the first to third channel layers include a first metal,
the second channel layer further includes a second metal different from the first metal, and
at least a portion of the first channel layer contacts the bit line.
20. The semiconductor memory device of claim 19 , further comprising:
first landing pads between the first vertical channel portions of the channel patterns and the first data storage patterns; and
second landing pads between the second vertical channel portions of the channel patterns and the second data storage patterns,
wherein the third channel layer contacts the gate insulating pattern,
a thickness of the first channel layer is equal to a thickness of the third channel layer, and a thickness of the second channel layer is greater than the thickness of the first or third channel layer, and
the first to third channel layers contact the first and second landing pads.