IP Library Granted Patent US 11,631,771
Granted Patent B2
US 11,631,771 · App. 17/367,637 · Granted Apr 18, 2023

Oxide semiconductor field effect transistor

Inventors: Chien-Ming Lai (Tainan, TW); Yen-Chen Chen (Tainan, TW); Jen-Po Huang (Tainan, TW); Sheng-Yao Huang (Kaohsiung, TW); Hui-Ling Chen (Kaohsiung, TW); Qinggang Xing (Singapore, SG); Ding-Lung Chen (Singapore, SG); Li Li Ding (Singapore, SG); Yao-Hung Liu (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7869H01L29/1037H01L29/4236H01L29/4966H01L29/51H01L29/66742
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Quick Facts
Patent No.
US 11,631,771
App. No.
17/367,637
Granted
Apr 18, 2023
Kind
B2
Abstract

An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Claims (21)

1. An oxide semiconductor field effect transistor, comprising:

a first insulating layer disposed on a substrate;

a source and a drain disposed in the first insulating layer;

a U-shaped channel layer sandwiched by the source and the drain without having any channel layers under the source and the drain and not covering the source and the drain; and

a metal gate disposed on the U-shaped channel layer, wherein the U-shaped channel layer comprises a plurality of oxide semiconductor layers, and wherein a top surface of the U-shaped channel layer and a top surface of the metal gate are coplanar.

2. The oxide semiconductor field effect transistor according to claim 1 , wherein the metal gate comprises a gate oxide layer, a metal layer and a low resistivity metal.

3. The oxide semiconductor field effect transistor according to claim 2 , further comprising:

a composite layer located between the gate oxide layer and the metal layer.

4. The oxide semiconductor field effect transistor according to claim 2 , wherein the gate oxide layer and the metal layer have U-shaped cross-sectional profiles.

5. The oxide semiconductor field effect transistor according to claim 1 , wherein a top surface of the metal gate is higher than top surfaces of the source and the drain.

6. The oxide semiconductor field effect transistor according to claim 1 , wherein a top surface of the U-shaped channel layer is higher than top surfaces of the source and the drain.

7. The oxide semiconductor field effect transistor according to claim 1 , further comprising:

an insulating layer disposed between the first insulating layer and the substrate.

8. The oxide semiconductor field effect transistor according to claim 7 , further comprising:

a back gate insulating layer disposed between the first insulating layer and the insulating layer.

9. The oxide semiconductor field effect transistor according to claim 7 , further comprising:

a back gate disposed right below the U-shaped channel layer and in the insulating layer.

10. The oxide semiconductor field effect transistor according to claim 9 , wherein the whole U-shaped channel layer vertically overlaps the back gate.

11. The oxide semiconductor field effect transistor according to claim 10 , wherein the back gate protrudes from the U-shaped channel layer.

12. The oxide semiconductor field effect transistor according to claim 1 , further comprising:

a cap layer conformally covering the source and the drain, and the first insulating layer blanketly covering the cap layer.

Priority Claims (1)
CN 201811041792.1 · Sep 7, 2018 · national
Continuity (2)
Continuation 16154644 · Oct 8, 2018
Related Publication 20210336059A1 · Oct 28, 2021