Fabrication of a vertical fin field effect transistor with an asymmetric gate structure

1. A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, comprising:

forming an outer gate structure around an outer wall of a tubular vertical fin, wherein the tubular vertical fin is directly in contact with a semiconductor substrate; and

forming an inner gate structure on an inner bottom spacer within an inner wall of the tubular vertical fin.

2. The method of claim 1 , further comprising forming an outer bottom spacer around an outer wall of a tubular vertical fin between the outer gate structure and the semiconductor substrate.

3. The method of claim 2 , wherein the outer gate structure includes an outer gate dielectric layer formed on the outer bottom spacer and the outer wall of the tubular vertical fin.

4. The method of claim 3 , wherein the outer gate structure includes an outer work function layer deposited over the outer gate dielectric layer.

5. The method of claim 4 , wherein the inner gate structure includes an inner gate dielectric layer formed on the inner bottom spacer and the inner wall of the tubular vertical fin.

6. The method of claim 5 , wherein the inner gate structure includes an inner work function layer deposited over the inner gate dielectric layer.

7. The method of claim 6 , wherein the inner work function layer and the outer work function layer are different materials.

8. The method of claim 6 , wherein the outer gate structure includes an outer gate fill layer formed on the outer work function layer, and the inner gate structure includes an inner gate fill layer formed on the inner work function layer.

9. The method of claim 8 , wherein the material of the outer gate fill layer and the material of the inner gate fill layer are selected from the group consisting of tungsten (W), titanium (Ti), molybdenum (Mo), cobalt (Co), and combinations thereof.

10. The method of claim 9 , wherein the material of the first gate fill layer is different from the material of the second gate fill layer.

11. A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, comprising:

forming a doped region in a substrate below a tubular vertical fin;

forming an outer gate structure on an outer bottom spacer on the substrate around an outer wall of the tubular vertical fin, wherein the outer bottom spacer provides electrical isolation between the doped region and the outer gate structure; and

forming an inner gate structure on an inner bottom spacer within an inner wall of the tubular vertical fin, wherein the inner bottom spacer provides electrical isolation between the doped region and the inner gate structure.

12. The method of claim 11 , further comprising an inner top spacer on the inner gate structure.

13. The method of claim 11 , further comprising an outer top spacer on the outer gate structure.

14. The method of claim 11 , wherein the material of the inner top spacer and the material of the outer top spacer are selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon boron carbonitride (SiBCN), and silicon oxycarbide (SiOC).

15. A vertical fin field effect transistor (vertical finFET) with a concentric gate structure, comprising:

a tubular vertical fin directly in contact with a doped region in a semiconductor substrate;

an outer bottom spacer around an outer wall of the tubular vertical fin;

an outer gate structure on the outer bottom spacer and the outer wall of the tubular vertical fin;

an inner bottom spacer within an inner wall of the tubular vertical fin; and

an inner gate structure on the inner bottom spacer and the inner wall of the tubular vertical fin.

16. The vertical finFET of claim 15 , wherein the inner gate structure and the outer gate structure are not electrically coupled together.

17. The vertical finFET of claim 15 , further comprising a top source drain on at least a portion of the top surface of the tubular vertical fin.

18. The vertical finFET of claim 17 , wherein the distance from the top surface of the tubular vertical fin to the substrate surface is greater within the tubular vertical fin than the distance from the top surface of the tubular vertical fin to the substrate surface outside the tubular vertical fin.

19. The vertical finFET of claim 15 , wherein the heights of the first gate structure and the second gate structure are unequal.

20. The vertical finFET of claim 15 , wherein the first gate structure includes a first gate dielectric layer, and the second gate structure includes a second gate dielectric layer, wherein the second gate dielectric layer is a different material than the first gate dielectric layer.