Access signal adjustment circuits and methods for memory cells in a cross-point array
Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
1. A memory device comprising:
a first two-terminal cross-point array comprising a plurality of two-terminal memory elements arranged in a plurality of slices; and
a target magnitude generator coupled to the first two-terminal cross-point array, the target magnitude generator comprising a second array of memory elements configured to condition an input voltage received at a first terminal of the second array to generate, at a second terminal of the second array, a target voltage magnitude for an access signal applied to one of the plurality of slices of the first two-terminal cross-point array.
2. The memory device of claim 1 , wherein each of the plurality of slices represents a group of the two-terminal memory elements formed by at least one word line.
3. The memory device of claim 2 , further comprising:
a word line voltage generator coupled to the two-terminal cross-point array, the word line voltage generator comprising the target magnitude generator and a positional voltage adjuster.
4. The memory device of claim 3 , further comprising:
a word line driver coupled between the word line voltage generator and the at least one word line.
5. The memory device of claim 1 , wherein the second array of memory elements comprises a first word line coupled to the first terminal and to a first memory element in the second array.
6. The memory device of claim 5 , wherein the second array of memory elements comprises a first bit line coupled to the second terminal and to the first memory element in the second array.
7. The memory device of claim 6 , wherein the first memory element in the second array to emulate operation of a corresponding memory element in the first array when the input voltage is received at the first terminal of the second array.
8. The memory device of claim 1 , wherein the target magnitude generator further comprises a disturb isolation circuit coupled to the second array of memory elements, the disturb isolation circuit to compensate for disturbances of a magnitude of a signal associated with a selected memory element of the second array of memory elements.
9. An apparatus comprising:
a substrate;
a first two-terminal cross-point array formed above the substrate, the first two-terminal cross-point array comprising a plurality of two-terminal memory elements arranged in a plurality of slices; and
a target magnitude generator formed on the substrate and coupled to the first two-terminal cross-point array, the target magnitude generator comprising a second array of memory elements configured to condition an input voltage received at a first terminal of the second array to generate, at a second terminal of the second array, a target voltage magnitude for an access signal applied to one of the plurality of slices of the first two-terminal cross-point array.
10. The apparatus of claim 9 , wherein each of the plurality of slices represents a group of the two-terminal memory elements formed by at least one word line.
11. The apparatus of claim 10 , further comprising:
a word line voltage generator coupled to the two-terminal cross-point array, the word line voltage generator comprising the target magnitude generator and a positional voltage adjuster.
12. The apparatus of claim 11 , further comprising:
a word line driver coupled between the word line voltage generator and the at least one word line.
13. The apparatus of claim 9 , wherein the second array of memory elements comprises a first word line coupled to the first terminal and to a first memory element in the second array.
14. The apparatus of claim 13 , wherein the second array of memory elements comprises a first bit line coupled to the second terminal and to the first memory element in the second array.
15. The apparatus of claim 14 , wherein the first memory element in the second array to emulate operation of a corresponding memory element in the first array when the input voltage is received at the first terminal of the second array.
16. The apparatus of claim 9 , wherein the target magnitude generator further comprises a disturb isolation circuit coupled to the second array of memory elements, the disturb isolation circuit to compensate for disturbances of a magnitude of a signal associated with a selected memory element of the second array of memory elements.
17. An integrated circuit comprising:
a logic layer formed on a substrate, the logic layer comprising a target magnitude generator; and
a memory comprising one or more layers formed above the substrate, the memory comprising a first two-terminal cross-point array comprising a plurality of two-terminal memory elements arranged in a plurality of slices,
wherein the target magnitude generator comprises a second array of memory elements configured to condition an input voltage received at a first terminal of the second array to generate, at a second terminal of the second array, a target voltage magnitude for an access signal applied to one of the plurality of slices of the first two-terminal cross-point array.
18. The integrated circuit of claim 17 , wherein the second array of memory elements comprises a first word line coupled to the first terminal and to a first memory element in the second array.
19. The integrated circuit of claim 18 , wherein the second array of memory elements comprises a first bit line coupled to the second terminal and to the first memory element in the second array.
20. The integrated circuit of claim 19 , wherein the first memory element in the second array to emulate operation of a corresponding memory element in the first array when the input voltage is received at the first terminal of the second array.