Three-dimensional memory devices and fabricating methods thereof

1. A method for forming a three-dimensional (3D) memory device, comprising:

forming an alternating dielectric stack on a substrate;

forming a first insulating layer on the alternating dielectric stack;

forming a hard mask layer on the first insulating layer;

forming a plurality of channel holes penetrating the alternating dielectric stack, the first insulating layer and the hard mask layer;

forming a channel structure in each channel hole;

forming a channel column structure on the channel structure in each channel hole;

removing the hard mask layer to expose an upper portion of a sidewall of each channel column structure;

trimming the upper portion of the sidewall of each channel column structure to reduce a diameter of the upper portion of each channel column structure in a lateral direction to form a channel plug; and

forming a top selective gate cut that penetrates a top selective gate structure formed between neighboring channel plugs.

2. The method of claim 1 , wherein forming the alternating dielectric stack comprises:

forming at least 32 dielectric layer pairs stacked in a vertical direction, wherein each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer.

3. The method of claim 1 , wherein forming the channel structure comprises:

forming a functional layer on a sidewall of the channel hole;

forming a channel layer covering a sidewall of the functional layer, the channel layer being in contact with an epitaxial layer on a bottom of the channel hole; and

forming a filling structure covering a sidewall of the channel layer and filling the channel hole.

4. The method of claim 3 , wherein forming the channel column structure comprises:

forming a recess in the channel structure to expose an upper portion of the channel layer;

forming a channel column structure in the recess; and

planarizing a top surface of the channel column structure.

5. The method of claim 1 , further comprising:

after forming the channel plugs, forming the top selective gate structure on the first insulating layer.

6. The method of claim 5 , wherein forming the top selective gate structure comprises:

forming a second insulating layer to cover exposed surfaces of the channel column structure and the channel plug;

forming a gate electrode layer on the first insulating layer and the second insulating layer;

removing an upper portion of the gate electrode layer to expose a top surface of the second insulating layer, the remaining portion of the gate electrode layer forming the top selective gate structure; and

forming a third insulating layer to cover the top selective gate structure.

7. The method of claim 6 , wherein forming the top selective gate cut comprises:

forming a trench between neighboring channel plugs, the trench penetrating the third insulating layer and the top selective gate structure to expose the first insulating layer; and

depositing a dielectric material in the trench to form the top selective gate cut.

8. The method of claim 5 , wherein forming the top selective gate cut comprises:

forming the top selective gate cut such that it has a wavy shape extending along a lateral direction.

9. The method of claim 8 , further comprises:

forming a pair of slits penetrating the alternating dielectric stack, the pair of slits being extended in parallel along the lateral direction;

forming a number N of rows of channel holes between the pair of slits, wherein each row of channel holes are arranged staggered with adjacent row of channel holes, and N is an even number; and

forming the top selective gate cut between number N/2 row of channel holes and number N/2+1 row of channel holes.

10. The method of claim 5 , further comprises:

forming the channel plug such that it has a diameter of a top surface within a range between 50 nm to 150 nm; and

forming the top selective gate cut such that it has a width of a top surface within a range between 10 nm to 110 nm;

wherein a minimum distance between the top selective gate cut and an adjacent channel plug is within a range between 10 nm to 60 nm.