IP Library Granted Patent US 10,998,182
Granted Patent B2
US 10,998,182 · App. 16/126,717 · Granted May 4, 2021

Semiconductor wafer and method of wafer thinning

Inventor: Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/02013B24B7/228B24B55/06H01L21/0209H01L21/02052H01L21/02057H01L21/304H01L21/6704H01L21/67051H01L21/76879H01L21/76898H01L21/78H01L22/14H01L23/544H01L2223/54453
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Quick Facts
Patent No.
US 10,998,182
App. No.
16/126,717
Granted
May 4, 2021
Kind
B2
Abstract

A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved.

Claims (21)

1. A method of thinning a semiconductor wafer, the method comprising:

providing a semiconductor wafer including a base material;

grinding a surface of the semiconductor wafer during a grinding phase using a grinder to remove a portion of the base material;

lifting the grinder off the surface of the semiconductor wafer only in a z axis during a separation phase; and

reversing movement of the grinder during the separation phase.

2. The method of claim 1 , further including repeating the grinding phase and separation phase.

3. The method of claim 1 , further including rinsing the surface of the semiconductor wafer during the grinding phase and separation phase to remove particles.

4. The method of claim 3 , wherein the rinsing is continuous.

5. The method of claim 3 , wherein the rinsing is pulsed.

6. A method of thinning a semiconductor wafer, the method comprising:

providing a semiconductor wafer including a base material;

grinding a surface of the semiconductor wafer during a first grinding phase using a grinder to remove a first portion of the base material;

lifting the grinder off the surface of the semiconductor wafer only in a z axis during a separation phase;

lowering the grinder back to the surface of the semiconductor wafer during the separation phase; and

grinding the surface of the semiconductor wafer during a second grinding phase using the grinder to remove a second portion of the base material.

7. The method of claim 6 , wherein the separation phase lasts between 3-10 seconds.

8. The method of claim 6 , wherein the surface of the semiconductor wafer is rinsed during the first grinding phase, the second grinding phase, and the separation phase.

9. The method of claim 6 , wherein the grinder is separated 3-10 micrometers from the surface of the semiconductor wafer during the separation phase.

10. The method of claim 6 , further comprising pausing rotational movement of the grinder during the separation phase.

11. The method of claim 6 , further comprising reversing rotational movement of the grinder during the separation phase.

12. The method of claim 6 , wherein a rotational movement of the grinder during the first grinding phase is opposite a rotational movement of the grinder during the second grinding phase.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047399, FRAME 0631 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064078/0001 →
SECURITY INTEREST Recorded Nov 1, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047399/0631 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2018
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 046831/0038 →
Continuity (2)
Continuation 15226362 · Aug 2, 2016
Related Publication 20190006169A1 · Jan 3, 2019