Method of forming a semiconductor device
In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to overlie a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a 2nd transistor that is formed external to the well region. A contact conductor may be applied to electrically and physically contact the first and 2nd gate conductors and to also overlie the boundary of the well region.
1. A semiconductor device comprising:
a semiconductor substrate having a first conductivity type;
a first doped region of a second conductivity type formed on a surface of the semiconductor substrate, the first doped region having a periphery with vertical sides abutting the semiconductor substrate at an outer boundary of the first doped region;
a first transistor formed in the first doped region, the first transistor having a first doped polysilicon gate conductor extending to overlie the boundary, the first doped polysilicon gate conductor having the first conductivity type;
a second transistor formed in the semiconductor substrate, the second transistor having a second doped polysilicon gate conductor extending to intersect the first doped polysilicon gate conductor, the second doped polysilicon gate conductor having the second conductivity type; and
a gate contact having a contact conductor formed physically contacting a first portion of the first doped polysilicon gate conductor, extending to physically contact a first portion of the second doped polysilicon gate conductor and physically contacting the first portion of the first doped polysilicon gate conductor at the intersect with the first portion of the second doped polysilicon gate conductor wherein the intersect is overlying the outer boundary.
2. The semiconductor device of claim 1 wherein the contact conductor has a first length that is greater than a first width of the contact conductor.
3. The semiconductor device of claim 2 wherein the first transistor includes a source contact having a source contact conductor having a second width and a second length wherein the first length is greater than the second length and also greater than the second width.
4. The semiconductor device of claim 1 further including an insulator overlying a second portion of the first doped polysilicon gate conductor that overlies a channel region of the first transistor, and overlying a second portion of the second doped polysilicon gate conductor that overlies a channel region of the second transistor, the insulator having an opening overlying the first portion of the first doped polysilicon gate conductor, overlying the first portion of the second doped polysilicon gate conductor, and overlying the outer boundary.
5. The semiconductor device of claim 4 wherein the first doped polysilicon gate conductor and the second doped polysilicon gate conductor extend to overlie the insulator, and intersect with each other overlying the outer boundary.
6. The semiconductor device of claim 1 wherein the first doped polysilicon gate conductor and the second doped polysilicon gate conductor are substantially only doped polysilicon.
7. The semiconductor device of claim 1 wherein the first and second doped polysilicon gate conductors substantially do not include a silicide or a salacide material.
8. The semiconductor device of claim 1 wherein the second transistor is external to the first doped region.
9. The semiconductor device of claim 1 further including a third transistor formed in the first doped region, the third transistor having a third doped polysilicon gate conductor of the first conductivity type.
10. The semiconductor device of claim 9 further including a fourth transistor formed in the semiconductor substrate and external to the first doped region, the fourth transistor having a fourth doped polysilicon gate conductor of the second conductivity type, the fourth doped polysilicon gate conductor extending to intersect the third doped polysilicon gate conductor.
11. The semiconductor device of claim 1 wherein one of the first doped polysilicon gate conductor or the second doped polysilicon gate conductor extends to overlie an interface between the semiconductor substrate and the periphery with the vertical sides of the first doped region.
12. The semiconductor device of claim 1 wherein a P-N junction is formed at the intersect of the second doped polysilicon gate conductor and the first doped polysilicon gate conductor.
13. The semiconductor device of claim 12 wherein the gate contact conductor forms a short across the P-N junction.