Segmented memory and operation
Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.
1. An apparatus, comprising:
a plurality of strings of series-connected memory cells, each string of series-connected memory cells of the plurality of strings of series-connected memory cells selectively connected to a common data line through a corresponding respective select gate;
a first set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and
a second set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.
2. The apparatus of claim 1 , wherein the second set of access lines are each connected to a control gate of a respective memory cell of each string of series-connected memory cells of a subset of the plurality of strings of series-connected memory cells comprising more than one string of series-connected memory cells of the plurality of strings of series-connected memory cells.
3. The apparatus of claim 1 , wherein the portion of the plurality of strings of series-connected memory cells is a first portion of the plurality of strings of series-connected memory cells, the apparatus further comprising a third set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of only a second portion of the plurality of strings of series-connected memory cells.
4. The apparatus of claim 3 , wherein the third set of access lines are each connected to a control gate of a respective memory cell of each string of series-connected memory cells of a subset of the plurality of strings of series-connected memory cells comprising more than one string of series-connected memory cells of the plurality of strings of series-connected memory cells.
5. The apparatus of claim 3 , wherein a union of the first portion of the plurality of strings of series-connected memory cells and the second portion of the plurality of strings of series-connected memory cells includes each string of series-connected memory cells of the plurality of strings of series-connected memory cells.
6. The apparatus of claim 1 , wherein the first set of access lines and the second set of access lines are mutually exclusive.
7. An apparatus, comprising:
an array of memory cells comprising a block of memory cells; and
a controller for access of memory cells of the array of memory cells;
wherein the block of memory cells comprises:
a plurality of strings of series-connected memory cells, wherein each string of series-connected memory cells of the plurality of strings of series-connected memory cells is selectively connected to a common data line by a respective select gate;
a first set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
a second set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells; and
a third set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of a second subset of the plurality of strings of series-connected memory cells.
8. The apparatus of claim 7 , wherein the plurality of strings of series-connected memory cells comprises more than two strings of series-connected memory cells.
9. The apparatus of claim 7 , wherein the second set of access lines and the third set of access lines are mutually exclusive.
10. The apparatus of claim 7 , wherein the first subset of the plurality of strings of series-connected memory cells comprises more than one string of series-connected memory cells.
11. The apparatus of claim 10 , wherein the second subset of the plurality of strings of series-connected memory cells comprises a same number of strings of series-connected memory cells as the first subset of the plurality of strings of series-connected memory cells.
12. The apparatus of claim 7 , wherein no access line of the second set of access lines is connected to a control gate of a memory cell of the second subset of the plurality of strings of series-connected memory cells, and wherein no access line of the third set of access lines is connected to a control gate of a memory cell of the first subset of the plurality of strings of series-connected memory cells.
13. An apparatus, comprising:
an array of memory cells comprising a block of memory cells; and
a controller for access of memory cells of the array of memory cells;
wherein the block of memory cells comprises:
a plurality of strings of series-connected memory cells, wherein each string of series-connected memory cells of the plurality of strings of series-connected memory cells is selectively connected to a common data line by a respective select gate;
a first set of access lines each coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
a second set of access lines each coupled to a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells;
a third set of access lines each coupled to a respective memory cell of each string of series-connected memory cells of a second subset of the plurality of strings of series-connected memory cells; and
a fourth set of access lines each coupled to a respective memory cell of each string of series-connected memory cells of a third subset of the plurality of strings of series-connected memory cells.
14. An apparatus, comprising:
an array of memory cells comprising a block of memory cells; and
a controller for access of memory cells of the array of memory cells;
wherein the block of memory cells comprises:
a plurality of strings of series-connected memory cells, wherein each string of series-connected memory cells of the plurality of strings of series-connected memory cells is selectively connected to a common data line by a respective select gate;
a first set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
a second set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells; and
a third set of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of a second subset of the plurality of strings of series-connected memory cells;
wherein a particular access line of the second set of access lines is connected to the control gates of its respective memory cells at a particular position of each string of series-connected memory cells of the first subset of the plurality of strings of series-connected memory cells; and
wherein a particular access line of the third set of access lines is connected to the control gates of its respective memory cells at the particular position of each string of series-connected memory cells of the second subset of the plurality of strings of series-connected memory cells.
15. The apparatus of claim 14 , wherein a number of strings of series-connected memory cells of the first subset of the plurality of strings of series-connected memory cells equals a number of strings of series-connected memory cells of the second subset of the plurality of strings of series-connected memory cells.
16. The apparatus of claim 14 , wherein each access line of the second set of access lines is formed at a same physical level as each access line of the third set of access lines.
17. The apparatus of claim 16 , wherein a first access line of the second set of access lines is formed between a first portion of a second access line of the second set of access lines and a second portion of the second access line of the second set of access lines.
18. The apparatus of claim 17 , wherein a first access line of the third set of access lines is formed between a first portion of a second access line of the third set of access lines and a second portion of the second access line of the third set of access lines.
19. The apparatus of claim 14 , wherein the particular position is a first particular position, wherein a different access line of the second set of access lines is connected to the control gates of its respective memory cells at a second particular position of each string of series-connected memory cells of the first subset of the plurality of strings of series-connected memory cells different than the first particular position, and wherein a different access line of the third set of access lines is connected to the control gates of its respective memory cells at the second particular position of each string of series-connected memory cells of the second subset of the plurality of strings of series-connected memory cells.
20. The apparatus of claim 19 , wherein the first particular position is at a different physical level than the second particular position.