Semiconductor device
A semiconductor device according to an embodiment includes a semiconductor substrate of a first conducting type. A pad is provided on the semiconductor substrate. An internal circuit is provided on the semiconductor substrate. An electrostatic discharge protection element is provided between the pad and the internal circuit. The electrostatic discharge protection element comprises a first well of a second conducting type, a second well of a first conducting type, and a first electrode layer of a second conducting type. The first well of a second conducting type is provided in a surface region of the semiconductor substrate. The second well of a first conducting type is provided inside the first well in the surface region of the semiconductor substrate. The first electrode layer of a second conducting type is provided inside the second well in the surface region of the semiconductor substrate.
1. A semiconductor device comprising:
a semiconductor substrate of a first conducting type;
a pad provided on the semiconductor substrate;
an internal circuit provided on the semiconductor substrate; and
an electrostatic discharge protection element provided between the pad and the internal circuit, the electrostatic discharge protection element comprising
a first well of a second conducting type provided in a surface region of the semiconductor substrate,
a second well of a first conducting type provided inside the first well in the surface region of the semiconductor substrate,
a first electrode layer of a second conducting type provided inside the second well in the surface region of the semiconductor substrate,
a third electrode layer of the first conducting type provided inside the second well in the surface region of the semiconductor substrate, and
an element isolation layer provided between the first electrode layer and the third electrode layer and isolating the first electrode layer and the third electrode layer.
2. The device of claim 1 , wherein the second well and the first electrode layer are included in a first diode configured to protect the internal circuit from electrostatic discharge.
3. The device of claim 1 , further comprising a memory cell array provided above the first and second wells.
4. The device of claim 2 , further comprising a memory cell array provided above the first and second wells.
5. The device of claim 3 , wherein the first and second wells included in the electrostatic discharge protection element have configurations substantially identical to configurations of first and second wells located below the memory cell army.
6. The device of claim 5 , wherein concentration profiles in a depth direction of the first and second wells included in the electrostatic discharge protection element are substantially identical to concentration profiles of the first and second wells located below the memory cell array.
7. The device of claim 1 , wherein the first electrode layer is electrically connected to a node between the pad and the internal circuit.
8. The device of claim 1 , wherein the second well is in an electrically floating state.
9. The device of claim 1 , further comprising a fourth well electrically connected to the first well, wherein
a voltage is applied to the fourth well.
10. A semiconductor device comprising:
a semiconductor substrate of a first conducting type;
a pad provided on the semiconductor substrate;
an internal circuit provided on the semiconductor substrate; and
an electrostatic discharge protection element provided between the pad and the internal circuit, the electrostatic discharge protection element comprising
a first well of a second conducting type provided in a surface region of the semiconductor substrate,
a second well of a first conducting type provided inside the first well in the surface region of the semiconductor substrate,
a first electrode layer of a second conducting type provided inside the second well in the surface region of the semiconductor substrate,
a third well of a second conducting type provided in a surface region of the semiconductor substrate, a surface region of the third well being different from the surface region where the first well is provided; and
at least one transistor provided on the third well, wherein
an impurity concentration of the second well is lower than an impurity concentration of the third well.
11. The device of claim 10 , wherein the second well and the first electrode layer are included in a first diode configured to protect the internal circuit from electrostatic discharge.
12. The device of claim 10 , further comprising a memory cell array (MCA) provided above the first and second wells.
13. The device of claim 10 , further comprising a second electrode layer of a first conducting type provided on the third well, wherein
the third well and the second electrode layer are included in a second diode configured to protect the internal circuit from electrostatic discharge.
14. The device of claim 13 , wherein the second electrode layer is electrically connected to a node between the pad and the internal circuit.
15. The device of claim 10 , wherein the second well is in an electrically floating state.
16. The device of claim 10 , further comprising a fourth well electrically connected to the first well, wherein
a voltage is applied to the fourth well.