IP Library › Granted Patent US 12,243,869
Granted Patent B2
US 12,243,869 · App. 17/350,852 · Granted Mar 4, 2025

Semiconductor device and semiconductor storage device

Inventors: Yasuhiro Suematsu (Yokohama, JP); Maya Inagaki (Yokohama, JP)
Assignee: Kioxia Corporation
H01L27/0255H01L23/5226H01L29/417H10B43/27H10B43/40
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Quick Facts
Patent No.
US 12,243,869
App. No.
17/350,852
Granted
Mar 4, 2025
Kind
B2
Abstract

In one embodiment, a semiconductor device includes substrate, a plurality of electrode layers provided above the substrate, and separated from each other in a first direction perpendicular to a surface of the substrate, and a first plug provided in the plurality of electrode layers. The device further includes first and second diffusion layers provided in the substrate, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit, a second plug provided at a position that overlaps with the first diffusion layer in planar view, and electrically connected with the first diffusion layer, and a third plug provided at a position that does not overlap with the first diffusion layer in planar view, and electrically connected with the first diffusion layer.

Claims (49)

1. A semiconductor device comprising:

a substrate in a first level;

a source line in a second level above the first level in a first direction perpendicular to a surface of the substrate;

a plurality of word lines provided in a third level above the second level in the first direction, the plurality of word lines being separated from each other in the first direction;

a first plug penetrating the plurality of word lines in the third level and electrically connected to the source line, a plurality of memory cells being provided between cross sections of the plurality of word lines and the first plug;

first and second diffusion layers provided in the substrate in the first level separately, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit;

a second plug provided in the second level and the third level at a position that overlaps with the first diffusion layer in the first direction, the second plug being electrically connected with the first diffusion layer;

a third plug provided in the second level and the third level at a position that does not overlap with the first diffusion layer and the second diffusion layer in the first direction, the third plug being electrically connected with the first diffusion layer;

a fourth plug provided in the second level and the third level at a position that overlaps with the second diffusion layer in the first direction, the fourth plug provided between the second plug and the third plug in a second direction intersecting the first direction;

a plurality of interconnects provided in a fourth level between the first level and the second level, the plurality of interconnects electrically connected to the third plug and the first diffusion layer that is electrically connected to the second plug;

a first upper interconnect provided above the third level in the first direction, and electrically connected with the second plug and the third plug; and

a second upper interconnect provided above the third level in the first direction, electrically connected with the fourth plug, and not electrically connected with the first upper interconnect,

wherein the first plug, the second plug, the third plug, and the fourth plug are provided in the third level.

2. The device of claim 1 , wherein

the first, second and third plugs extend in the first direction, and

the third plug is provided at a position that overlaps with the second diffusion layer in the first direction.

3. The device of claim 1 , wherein

the first, second and third plugs extend in the first direction, and

the third plug is provided at a position that overlaps with neither the first nor second diffusion layer in the first direction.

4. The device of claim 1 , wherein the first diffusion layer is surrounded by the second diffusion layer in a plane orthogonal to the first direction.

5. The device of claim 4 , wherein

the first diffusion layer includes a first diffusion region and a second diffusion region, and

the first diffusion region and the second diffusion region are surrounded by the second diffusion layer in the plane orthogonal to the first direction.

6. The device of claim 5 , wherein the first diffusion region and the second diffusion region extend in the second direction parallel to the surface of the substrate, and are separated from each other in a third direction that is parallel to the surface of the substrate and different from the second direction, each of the first diffusion region and the second diffusion region being surrounded by the second diffusion layer.

7. The device of claim 1 , wherein

the first diffusion layer extends in the second direction parallel to the surface of the substrate; and

the second diffusion layer includes a first portion extending in the second direction, and includes at least one of a second portion connected with one end of the first portion and extending in a third direction that is parallel to the surface of the substrate and different from the second direction, and a third portion connected with another end of the first portion and extending in the third direction.

8. The device of claim 7 , wherein the fourth plug is electrically connected with the second diffusion layer,

wherein

the third plug extends in the first direction, and is provided at a position that overlaps with the first portion of the second diffusion layer in the first direction, and

the fourth plug extends in the first direction, and is provided at a position that overlaps with the second or third portion of the second diffusion layer in the first direction.

9. The device of claim 7 , wherein the second diffusion layer further includes a fourth portion connected to the second and third portions and extending in the second direction.

10. The device of claim 9 , wherein the first and fourth portions are provided to be separated from each other in the third direction.

11. The device of claim 7 , further comprising:

a first interconnect provided above the second plug in the first direction and electrically connected with the second plug; and

a second interconnect provided above the third plug in the first direction and electrically connected with the third plug.

12. The device of claim 11 , wherein the first and second interconnects extend in the second direction, and are provided to be separated from each other in the third direction.

13. The device of claim 11 , further comprising:

a third interconnect provided between the substrate and the second plug in the first direction, and electrically connected with the second plug; and

a fourth interconnect provided between the substrate and the third plug in the first direction, and electrically connected with the third plug;

wherein the plurality of word lines include a first word line provided above the third and fourth interconnects in the first direction,

wherein the plurality of word lines include a second word line provided between the first electrode layer and the first and second interconnects in the first direction,

wherein the device further comprises:

a fifth interconnect provided between the word line layer and the first and second interconnects; and

a sixth interconnect provided between the first word line and the third and fourth interconnects, and

wherein the first plug includes:

a semiconductor layer penetrating through the first and second word lines, one end of the semiconductor layer being electrically connected with the fifth interconnect, the other end of the semiconductor layer being electrically connected with the sixth interconnect;

a first charge storage layer provided at a position where the first word line crosses the semiconductor layer; and

a second charge storage layer provided at a position where the second word line crosses the semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2021
From: SUEMATSU, YASUHIRO; INAGAKI, MAYA
To: KIOXIA CORPORATION
Reel/Frame 057502/0868 →
Priority Claims (1)
JP 2021-035502 · Mar 5, 2021 · national
Continuity (1)
Related Publication 20220285337A1 · Sep 8, 2022
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