IP Library › Granted Patent US 10,355,894
Granted Patent B2
US 10,355,894 · App. 16/128,348 · Granted Jul 16, 2019

Simplified 3-phase mapping and coding

Inventor: George Alan Wiley (San Diego, CA)
Assignee: QUALCOMM Incorporated
H04L27/2057H04L25/0272H04L25/49
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Quick Facts
Patent No.
US 10,355,894
App. No.
16/128,348
Granted
Jul 16, 2019
Kind
B2
Abstract

Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus. An apparatus has a bus interface, a 3-phase encoder, and a processing circuit that can configure the 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols, transmit a first three-phase signal representative of the sequence of two-bit symbols on each of the three wires. The processing circuit may be configured to configure the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols. Three-phase signal representative of the sequence of two-bit symbols or sequence of three-bit symbols on each of three wires, where a three-phase signal is in a different phase on each wire when transmitted, and a transition in signaling state occurs between transmission of each pair of symbols.

Claims (58)

1. A method for data communication, comprising:

configuring a 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols;

transmitting a first three-phase signal that is representative of the sequence of two-bit symbols on each of three wires, wherein the first three-phase signal is in a different phase on each wire when each symbol in the sequence of two-bit symbols is transmitted, and wherein a transition in signaling state in one or more wires occurs between transmission of each pair of symbols in the sequence of two-bit symbols;

configuring the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols; and

transmitting a second three-phase signal that is representative of the sequence of three-bit symbols on each of the three wires, wherein the second three-phase signal is in a different phase on each wire when each symbol in the sequence of three-bit symbols is transmitted, and wherein a transition in signaling state in at least one wire occurs between transmission of each pair of symbols in the sequence of three-bit symbols.

2. The method of claim 1 , wherein signaling states of the three wires are defined by polarity and direction of rotation when the 3-phase encoder is configured for the first mode of operation.

3. The method of claim 2 , wherein each symbol in the sequence of two-bit symbols selects between four transitions that are available from each signaling state of the three wires when the 3-phase encoder is configured for the first mode of operation.

4. The method of claim 2 , wherein each symbol in the sequence of two-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, and a second bit that defines phase rotation associated with the next signaling state.

5. The method of claim 2 , wherein each symbol in the sequence of three-bit symbols selects between five transitions that are available from each signaling state when the 3-phase encoder is configured for the second mode of operation.

6. The method of claim 5 , wherein each symbol in the sequence of three-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, a second bit that defines phase rotation associated with the next signaling state, and a third bit that determines whether the next signaling state involves only a polarity switch from the current signaling state.

7. The method of claim 1 , further comprising:

determining presence of a misalignment of the three wires involving two or more wires;

inverting a phase rotation bit of each symbol in the sequence of two-bit symbols when the misalignment of the three wires is determined to affect phase relationships between signals carried on the three wires when the 3-phase encoder is configured for the first mode of operation; and

inverting a phase rotation bit of each symbol in the sequence of three-bit symbols when the misalignment of the three wires is determined to affect phase relationships between signals carried on the three wires when the 3-phase encoder is configured for the second mode of operation.

8. The method of claim 7 , wherein the presence of the misalignment of the three wires is determined during a training transmission.

9. A data communication apparatus, comprising:

a bus interface configured to couple the apparatus to three wires of a communication link;

a 3-phase encoder adapted to provide sequences of symbols used to configure three-phase signals transmitted over the three wires; and

a processing circuit configured to:

configure the 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols;

transmit a first three-phase signal that is representative of the sequence of two-bit symbols on each of the three wires, wherein the first three-phase signal is in a different phase on each wire when each symbol in the sequence of two-bit symbols is transmitted, and wherein a transition in signaling state in one or more wires occurs between transmission of each pair of symbols in the sequence of two-bit symbols;

configure the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols; and

transmit a second three-phase signal that is representative of the sequence of three-bit symbols on each of the three wires, wherein the second three-phase signal is in a different phase on each wire when each symbol in the sequence of three-bit symbols is transmitted, and wherein a transition in signaling state in at least one wire occurs between transmission of each pair of symbols in the sequence of three-bit symbols.

10. The apparatus of claim 9 , wherein signaling states of the three wires are defined by polarity and direction of rotation when the 3-phase encoder is configured for the first mode of operation.

11. The apparatus of claim 10 , wherein each symbol in the sequence of two-bit symbols selects between four transitions that are available from each signaling state when the 3-phase encoder is configured for the first mode of operation.

12. The apparatus of claim 10 , wherein each symbol in the sequence of two-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, and a second bit that defines phase rotation associated with the next signaling state.

13. The apparatus of claim 10 , wherein each symbol in the sequence of three-bit symbols selects between five transitions that are available from each signaling state when the 3-phase encoder is configured for the second mode of operation.

14. The apparatus of claim 13 , wherein each symbol in the sequence of three-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, a second bit that defines phase rotation associated with the next signaling state, and a third bit that determines whether the next signaling state involves only a polarity switch from the current signaling state.

15. The apparatus of claim 9 , wherein the processing circuit is further configured to:

determine presence of a misalignment of the three wires involving two or more wires;

invert a phase rotation bit of each symbol in the sequence of two-bit symbols when the misalignment of the three wires is determined to affect phase relationships between signals carried on the three wires when the 3-phase encoder is configured for the first mode of operation; and

invert a phase rotation bit of each symbol in the sequence of three-bit symbols when the misalignment of the three wires is determined to affect phase relationships between signals carried on the three wires when the 3-phase encoder is configured for the second mode of operation.

16. The apparatus of claim 15 , wherein the presence of the misalignment of the three wires is determined during a training transmission.

17. A processor-readable storage medium having one or more instructions which, when executed by at least one processor of a processing circuit, cause the processing circuit to:

configure a 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols;

transmit a first three-phase signal that is representative of the sequence of two-bit symbols on each of three wires, wherein the first three-phase signal is in a different phase on each wire when each symbol in the sequence of two-bit symbols is transmitted, and wherein a transition in signaling state in one or more wires occurs between transmission of each pair of symbols in the sequence of two-bit symbols;

configure the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols; and

transmit a second three-phase signal that is representative of the sequence of three-bit symbols on each of the three wires, wherein the second three-phase signal is in a different phase on each wire when each symbol in the sequence of three-bit symbols is transmitted, and wherein a transition in signaling state in at least one wire occurs between transmission of each pair of symbols in the sequence of three-bit symbols.

18. The storage medium of claim 17 , wherein signaling states of the three wires are defined by polarity and direction of rotation when the 3-phase encoder is configured for the first mode of operation.

19. The storage medium of claim 18 , wherein each symbol in the sequence of two-bit symbols selects between four transitions that are available from each signaling state of the three wires when the 3-phase encoder is configured for the first mode of operation.

20. The storage medium of claim 18 , wherein each symbol in the sequence of two-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, and a second bit defines phase rotation associated with the next signaling state.

21. The storage medium of claim 18 , wherein each symbol in the sequence of three-bit symbols selects between five transitions that are available from each signaling state when the 3-phase encoder is configured for the second mode of operation.

22. The storage medium of claim 21 , wherein each symbol in the sequence of three-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, a second bit defines phase rotation associated with the next signaling state, and a third bit that determines whether the next signaling state involves only a polarity switch from the current signaling state.

23. The storage medium of claim 17 , further comprising:

determine presence of a misalignment of the three wires involving two or more wires;

invert a phase rotation bit of each symbol in the sequence of two-bit symbols when the misalignment of the three wires is determined to affect phase relationships between signals carried on the three wires when the 3-phase encoder is configured for the first mode of operation; and

invert a phase rotation bit of each symbol in the sequence of three-bit symbols when the misalignment of the three wires is determined to affect phase relationships between signals carried on the three wires when the 3-phase encoder is configured for the second mode of operation.

24. The storage medium of claim 23 , wherein the presence of the misalignment of the three wires is determined during a training transmission.

25. An apparatus comprising:

means for configuring a 3-phase encoder, wherein in a first mode of operation, data is encoded in a sequence of two-bit symbols, and wherein in a second mode of operation, data is encoded in a sequence of three-bit symbols; and

means for transmitting three-phase signals on each of three wires,

wherein in the first mode of operation, a first three-phase signal that is representative of the sequence of two-bit symbols is transmitted on each of the three wires, wherein the first three-phase signal is in a different phase on each wire when each symbol in the sequence of two-bit symbols is transmitted, and wherein a transition in signaling state in one or more wires occurs between transmission of each pair of symbols in the sequence of two-bit symbols, and

wherein in the second mode of operation, a second three-phase signal that is representative of the sequence of three-bit symbols is transmitted on each of the three wires, wherein the second three-phase signal is in a different phase on each wire when each symbol in the sequence of three-bit symbols is transmitted, and wherein a transition in signaling state in one or more wires occurs between transmission of each pair of symbols in the sequence of three-bit symbols.

26. The apparatus of claim 25 , wherein signaling states of the three wires are defined by polarity and direction of rotation when the 3-phase encoder is configured for the first mode of operation.

27. The apparatus of claim 26 , wherein each symbol in the sequence of two-bit symbols selects between four transitions that are available from each signaling state when the 3-phase encoder is configured for the first mode of operation.

28. The apparatus of claim 26 , wherein each symbol in the sequence of two-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, and a second bit defines phase rotation associated with the next signaling state.

29. The apparatus of claim 26 , wherein each symbol in the sequence of three-bit symbols selects between five transitions that are available from each signaling state when the 3-phase encoder is configured for the second mode of operation.

30. The apparatus of claim 29 , wherein each symbol in the sequence of three-bit symbols comprises a first bit that determines whether a next signaling state has a different polarity than a current signaling state, a second bit defines phase rotation associated with the next signaling state, and a third bit that determines whether the next signaling state involves only a polarity switch from the current signaling state.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2018
From: WILEY, GEORGE ALAN
To: QUALCOMM INCORPORATED
Reel/Frame 047522/0884 →
Continuity (2)
Provisional Application 62562314 · Sep 22, 2017
Related Publication 20190097852A1 · Mar 28, 2019
Cited By (1)
US 12,652,199