IP Library Granted Patent US 10,826,385
Granted Patent B2
US 10,826,385 · App. 16/128,916 · Granted Nov 3, 2020

Power factor correction circuit with calculated duty compensation and driving method thereof

Inventors: Jintae Kim (Seongnam-si, KR); Hangseok Choi (Yongin-si, KR); SangCheol Moon (Bucheon-si, KR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02M1/42H02M1/4225H02M7/06Y02B70/10Y02P80/10
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Quick Facts
Patent No.
US 10,826,385
App. No.
16/128,916
Granted
Nov 3, 2020
Kind
B2
Abstract

Provided is a power factor correction circuit including an inductor having one end to which an input voltage is applied; a power switch connected between another end of the inductor and the ground, and configured to control an output of the power factor correction circuit; and a power factor correction controller configured to calculate a duty of the power switch on the basis of an output detection voltage corresponding to the output and an inductor current flowing through the inductor, calculate conduction-period information regarding a conduction period in which the inductor current flows in one switching cycle of the power switch, and compensate the calculated duty on the basis of the conduction-period information.

Claims (35)

1. A controller for a power factor correction (PFC) circuit, the controller comprising:

a time demodulator configured to generate a conduction detection signal in response to a zero-current detection signal, the conduction detection signal indicating a zero-current duration of an inductor current; and

a duty controller configured to generate conduction-period information in response to the conduction detection signal, the conduction-period information being associated with a conduction period in which the inductor current flows through a power switch, and to generate a duty control signal in response to the conduction-period information,

wherein a value of the conduction-period information decreases as a value of the conduction detection signal increases when the PFC circuit operates in a first mode and is substantially constant when the PFC circuit operates in a second mode.

2. The controller of claim 1 , wherein the first mode is a discrete conduction mode (DCM) and the second mode is a continuous conduction mode (CCM), and the inductor current keeps having a magnitude greater than zero during an entire switching cycle of the power switch when the PFC circuit operates in the CCM.

3. The controller of claim 1 , wherein the duty controller comprises:

a conduction period calculator circuit generating the conduction-period information in response to the conduction detection signal; and

a duty compensator circuit generating the duty control signal in response to the conduction-period information and duty information.

4. The controller of claim 1 , wherein the duty controller calculates the conduction-period information by subtracting the value of the conduction detection voltage from a predetermined reference value.

5. The controller of claim 1 , wherein the time demodulator generates the conduction detection signal by sampling a reference signal synchronized with a switching frequency of the power switch at a detected zero-cross time and holding a sampled reference signal to generate the conduction detection voltage.

6. The controller of claim 1 , wherein the conduction-period information has a maximum value when the PFC circuit operates in the second mode.

7. The controller of claim 1 , further comprising:

a comparator comparing the duty control signal with a predetermined reference signal synchronized with a switching frequency of the power switch; and

a flip-flop generating a gate signal to control the power switch in response to a comparison result.

8. The controller of claim 1 , wherein, when the PFC circuit operates in the first mode, the duty controller decreases a value of the duty control signal by decreasing the value of the conduction-period information as the zero-current duration of the inductor current increases.

9. The controller of claim 3 , wherein duty controller further comprises a duty calculator generating the duty information in response to line-current information and an output error voltage, the line-current information being associated with an average inductor current.

10. The controller of claim 5 , wherein the reference signal has a sawtooth waveform that decreases with a predetermined slope in a switching cycle of the power switch.

11. The controller of claim 5 , wherein the reference signal has a sawtooth waveform that increases with a predetermined slope in a switching cycle of the power switch.

12. The controller of claim 9 , wherein the duty compensator circuit generates the duty control signal by multiplying a value of the duty information by the value of the conduction-period information.

13. A method of controlling a power factor correction (PFC) circuit, the method comprising:

generating a conduction detection signal in response to a zero-current detection signal, the conduction detection signal indicating a zero-current duration of an inductor current;

decreasing a value of the conduction-period information a value of the conduction detection signal increases when the PFC circuit operates in a first mode and keeping the value of the conduction-period information substantially constant when the PFC circuit operates in a second mode, the conduction-period information being associated with a conduction period in which the inductor current flows through a power switch; and

generating a duty control signal in response to the conduction-period information.

14. The method of claim 13 , wherein the first mode is a discrete conduction mode (DCM) and the second mode is a continuous conduction mode (CCM), and the inductor current keeps having a magnitude greater than zero during an entire switching cycle of the power switch when the PFC circuit operates in the CCM.

15. The method of claim 13 , further comprising:

calculating the conduction-period information by subtracting the value of the conduction detection voltage from a predetermined reference value.

16. The method of claim 13 , further comprising sampling a reference signal synchronized with a switching frequency of the power switch at a detected zero-cross time and holding a sampled reference signal to generate the conduction detection voltage.

17. The method of claim 13 , further comprising decreasing a value of the duty control signal by decreasing the value of the conduction-period information as the zero-current duration of the inductor current increases when the PFC circuit operates in the first mode.

18. The method of claim 16 , wherein the reference signal has a sawtooth waveform that increases with a predetermined slope in a switching cycle of the power switch.

19. A power converter comprising:

an inductor having a first end to which an input voltage is applied and a second end;

a power switch coupled between the second end of the inductor and a ground, the power switch being configured to control an output of the power converter; and

a power factor correction (PFC) controller configured to generate a conduction detection signal in response to a zero-current detection signal, the conduction detection signal indicating a zero-current duration of an inductor current, to generate conduction-period information in response to the conduction detection signal, the conduction-period information being associated with a conduction period in which the inductor current flows through a power switch, and to generate a duty control signal in response to the conduction-period information,

wherein a value of the conduction-period information decreases as a value of the conduction detection signal increases when the power converter operates in a first mode and is substantially constant when the power converter operates in a second mode.

20. The power converter of claim 19 , wherein, when the power converter operates in the first mode, the PFC controller decreases a value of the duty control signal by decreasing the value of the conduction-period information as the zero-current duration of the inductor current increases.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047399, FRAME 0631 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064078/0001 →
SECURITY INTEREST Recorded Nov 1, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047399/0631 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2018
From: FAIRCHILD KOREA SEMICONDUCTOR LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 047523/0141 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2018
From: KIM, JINTAE; CHOI, HANGSEOK; MOON, SANGCHEOL
To: FAIRCHILD KOREA SEMICONDUCTOR LTD.
Reel/Frame 046853/0813 →
Cited By (1)
US 12,638,479