System and apparatus to provide current compensation

1. An apparatus comprising:

a first current path including a first transistor that includes a first gate, a first drain and a first source, and a second transistor that includes a second gate, a second drain and a second source, the first drain coupled to the second drain;

a second current path including a third transistor that includes a third gate, a third drain, and a third source, and a fourth transistor that includes a fourth gate a fourth drain and a fourth source, the third source coupled to the first source and the third gate, the third drain coupled to the fourth drain, the fourth source coupled to the fourth gate and the second source; and

a current mirror including a fifth transistor that includes a fifth gate, a fifth drain, and a fifth source, and a sixth transistor that includes a sixth gate, a sixth drain, and a sixth source, the fifth drain coupled to the third drain, the sixth gate and the fifth gate, the sixth drain coupled to the second drain, the fifth source coupled to the sixth source and the fourth source, wherein a first ratio exists between the first transistor and the third transistor, a second ratio exists between the second transistor and the fourth transistor, and a third ratio exists between the fifth transistor and the sixth transistor, the third ratio greater than or equal to the second ratio, the second ratio greater than or equal to the first ratio.

2. The apparatus of claim 1 , wherein the first transistor and the third transistor are PMOS transistors and the second transistor, fourth transistor, fifth transistor, and sixth transistor are NMOS transistors.

3. The apparatus of claim 1 , wherein the first ratio is based on a first channel width of the first transistor and a second channel width of the third transistor, the second ratio is based on a third channel width of the second transistor and a fourth channel width of the fourth transistor, and the third ratio is based on a fifth channel width of the fifth transistor and a sixth channel width of the sixth transistor.

4. The apparatus of claim 1 , wherein the first current path is coupled to the second current path and the current mirror.

5. The apparatus of claim 1 , wherein the second current path is coupled to the first current path and the current mirror.

6. An apparatus comprising:

a regulator configured to regulate a flow of current through a power converter using a first transistor and a second transistor;

a sensor configured to:

detect a first current associated with the first transistor and a second current associated with the second transistor, wherein the first current is detected with a third transistor via a current mirroring configuration and the second current is detected with a fourth transistor via the current mirroring configuration; and

determine a difference between the first current and the second current; and

an adaptive compensation circuit configured to adjust a third current through an output of the power converter based on the difference between the first current and the second current.

7. The apparatus of claim 6 , wherein the first current is a first leakage current and the second current is a second leakage current.

8. The apparatus of claim 7 , wherein the first leakage current is a first current that flows out of a first drain of the first transistor and the second leakage current is a second current that flows into a second drain of the second transistor.

9. The apparatus of claim 6 , wherein the adjustment is to deduct the difference between the first current and the second current from the output of the power converter.

10. The apparatus of claim 6 , wherein the adaptive compensation circuit increases an efficiency of the power converter.

11. The apparatus of claim 6 , wherein the adaptive compensation circuit may adjust the third current when the first transistor and the second transistor are off.

12. A system comprising:

a regulator coupled to an output of a power converter configured to regulate current in the power converter;

a sensor configured to:

detect a first current associated with a first transistor and a second current associated with a second transistor, wherein the first current is detected with a third transistor via a current mirroring configuration and the second current is detected with a fourth transistor via the current mirroring configuration; and

determine a difference between the first current and the second current; and

an adaptive compensation circuit to adjust a third current through the output of the power converter based on the difference between the first current and the second current.

13. The system defined in claim 12 , wherein the first current is a first leakage current and the second current is a second leakage current.

14. The system of claim 13 , wherein the first leakage current is a first current that flows out of a first drain of the first transistor and the second leakage current is a second current that flows into a second drain of the second transistor.

15. The system of claim 12 , wherein the adjustment is to deduct the difference between the first current and the second current from the output of the power converter.

16. The system of claim 12 , wherein the adaptive compensation circuit increases an efficiency of the power converter.

17. The system of claim 12 , wherein the adaptive compensation circuit may adjust the third current when the first transistor and the second transistor are off.

18. The system of claim 12 , wherein the regulator includes a set of synchronous transistors, including a high-side transistor and a low-side transistor.

19. The system of claim 18 , wherein the low-side transistor may be a diode.