IP Library Patent Application 16130835
Patent Application
App. No. 16/130,835

DIE BONDING TO A BOARD

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Quick Facts
Patent No.
US None
App. No.
16/130,835
Abstract

An apparatus for bonding die to a board includes a circuit board having a solderable layer and a plurality of die bonded to the circuit board using at least three respective layers. Each of the at least three respective layers includes an inner layer, a first alloy of material from an outer layer and the solderable layer of the circuit board, and a second alloy of material from the outer layer and the solderable layer of the circuit board. Melting temperatures of the first alloy and the second alloy are higher than reflow temperatures of the outer layer and the solderable layer of the circuit board.

Claims (50)

1 . An apparatus, comprising:

a first solderable layer on a surface of a ceramic or substrate board or a metal lead frame;

first circuitry comprising:

a first solderable die surface on a first die comprising a first plurality of metal layers wherein an outer layer comprises a silver and tin first alloy having a silver composition that is less than 7 percent by weight and wherein an inner layer next to the outer layer comprises one of titanium, nickel or silver; and

a second alloy having a subsequent melting temperature that is higher than a first reflow temperature required to adhere the first die to the first solderable layer of the board, wherein the second alloy bonds the first alloy to the first solderable layer of the surface of the board to hold the first die to the board, and

second circuitry comprising:

a second solderable die surface on a second die comprising a third alloy,

wherein the first and second circuitry are configured to control operations of the apparatus.

2 . The apparatus of claim 1 , wherein the second alloy has a melting temperature that will not completely melt during subsequent reflow process at the first reflow temperature used to add the second circuitry.

3 . The apparatus of claim 1 , wherein the first solderable layer of the ceramic or substrate board or metal lead frame comprises at least one of copper, silver and tin.

4 . The apparatus of claim 1 , wherein the subsequent melting temperature of the second alloy is approximately at least 15 degrees C. higher than the first reflow temperature.

5 . The apparatus of claim 1 , wherein:

the first reflow temperature is in a range of from 220 degrees C. to 260 degrees C.; and

the subsequent melting temperature of the second alloy is higher than 260 degrees C.

6 . An apparatus, comprising:

a circuit board having a solderable layer;

a plurality of die bonded to the circuit board using at least three respective layers, each of the at least three respective layers comprising:

an inner layer;

a first alloy of material from an outer layer and the solderable layer of the circuit board; and

a second alloy of material from the outer layer and the solderable layer of the circuit board,

wherein melting temperatures of the first alloy and the second alloy are higher than reflow temperatures of the outer layer and the solderable layer of the circuit board.

7 . The apparatus of claim 6 , wherein:

the circuit board comprises a ceramic board.

8 . The apparatus of claim 6 , wherein:

the circuit board comprises a metal lead frame.

9 . The apparatus of claim 6 , wherein:

the inner layer of the at least three respective layers comprises silver.

10 . The apparatus of claim 9 , wherein:

the outer layer comprises tin.

11 . The apparatus of claim 10 , wherein:

the first alloy comprises an alloy of silver and tin.

12 . The apparatus of claim 9 , wherein:

the solderable layer of the circuit board comprises at least one of copper, nickel, tin, and silver.

13 . The apparatus of claim 12 , wherein:

the solderable layer of the circuit board comprises a metallic layer of one of copper, tin, and silver.

14 . The apparatus of claim 12 , wherein:

the solderable layer of the circuit board comprises an alloy formed of two or more metals.

15 . The apparatus of claim 6 , wherein:

the melting temperatures of the first alloy and the second alloy are at least 15 degrees C. higher than the reflow temperatures of the inner layer and the outer layer.

16 . The apparatus of claim 6 , wherein:

the reflow temperatures of the inner layer and the outer layer are in a range of from 220 degrees C. to 260 degrees C.; and

the melting temperatures of the first alloy and the second alloy are higher than 260 degrees C.

17 . The apparatus of claim 6 , wherein:

the solderable layer of the circuit board comprises copper.

18 . The apparatus of claim 6 , wherein:

the solderable layer of the circuit board comprises a plurality of layers.

19 . The apparatus of claim 18 , wherein:

the plurality of layers of the solderable layer of the circuit board comprise at least one metal layer.

20 . The apparatus of claim 18 , wherein:

the plurality of layers of the solderable layer of the circuit board comprise at least one metal alloy layer.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047399, FRAME 0631 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064078/0001 →
SECURITY INTEREST Recorded Nov 1, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047399/0631 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2018
From: SEDDON, MICHAEL J.; CARNEY, FRANCIS J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 046872/0126 →