IP Library › Granted Patent US 10,824,211
Granted Patent B2
US 10,824,211 · App. 16/131,477 · Granted Nov 3, 2020

Semiconductor device

Inventors: Akihiro Hanada (Tokyo, JP); Hajime Watakabe (Tokyo, JP); Kazufumi Watabe (Tokyo, JP)
Assignee: Japan Display Inc.
G06F1/26H01L27/1225H01L27/1237H01L27/1248H01L27/1251H02J13/0062H04L41/069H04L47/2416H04L67/12H01L29/42384H01L29/513H01L29/517H01L29/518H01L29/7869H01L29/78606H01L29/78633H01L29/78675H01L2029/42388H04Q9/02H04Q2209/826
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Quick Facts
Patent No.
US 10,824,211
App. No.
16/131,477
Granted
Nov 3, 2020
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

Claims (41)

1. A semiconductor device comprising:

an insulating substrate;

a metal oxide semiconductor layer positioned above the insulating substrate;

a first insulating film formed of a silicon nitride and positioned between the insulating substrate and the metal oxide semiconductor layer;

a block layer positioned between the first insulating film and the metal oxide semiconductor layer, the block layer being formed of aluminum oxide;

a second insulating film formed of a silicon oxide between the first insulating film and the block layer;

a third insulating film formed of a silicon oxide, positioned above the metal oxide semiconductor layer, and covering the metal oxide semiconductor layer;

an interlayer insulating film formed of a silicon oxide between the first insulating film and the insulating substrate; and

a first gate electrode located between the first insulating film and the interlayer insulating film, and facing the metal oxide semiconductor layer via the first insulating film and the second insulating film, wherein

the second insulating film contacts a lower surface of the block layer, and

the third insulating film is formed thicker than the first insulating film, the second insulating film, and the interlayer insulating film.

2. The semiconductor device of claim 1 , further comprising a silicon semiconductor layer positioned above the insulating substrate.

3. The semiconductor device of claim 2 , wherein the block layer continuously extends to a position opposed to the silicon semiconductor layer and a position opposed to the metal oxide semiconductor layer.

4. The semiconductor device of claim 2 , wherein the metal oxide semiconductor layer is in a position which is not opposed to the silicon semiconductor layer with the first insulating film and the second insulating film interposed therebetween, and

the block layer continuously extends from a position opposed to the silicon semiconductor layer to a position opposed to the metal oxide semiconductor layer.

5. The semiconductor device of claim 4 , wherein the block layer is thicker in an area opposed to the metal oxide semiconductor layer than in an area opposed to the silicon semiconductor layer.

6. The semiconductor device of claim 5 , wherein the block layer includes an upper surface of an area opposed to the silicon semiconductor layer which contacts a lower surface of the metal oxide semiconductor layer.

7. The semiconductor device of claim 2 , wherein the block layer is formed as an island opposed to the entire surface of the metal oxide semiconductor layer without being opposed to the silicon semiconductor layer.

8. The semiconductor device of claim 2 , further comprising:

a first second gate electrode opposed to the silicon semiconductor layer; wherein

the second gate electrode positioned in the same layer in which the first gate electrode is disposed, the first gate electrode formed of the same material used for the first second gate electrode.

9. The semiconductor device of claim 8 , wherein the interlayer insulating film is positioned between the silicon semiconductor layer and the first insulating film and contacts an upper surface of the silicon semiconductor layer and a lower surface of the first insulating film.

10. The semiconductor device of claim 2 , further comprising:

a second gate electrode opposed to the silicon semiconductor layer; wherein

the second gate electrode formed of the same material used for the first gate electrode.

11. The semiconductor device of claim 10 , wherein the second gate electrode contacts an upper surface of the interlayer insulating film and is covered with the first insulating film, and

the first gate electrode contacts the upper surface of the interlayer insulating film and is covered with the first insulating film.

12. The semiconductor device of claim 10 , wherein the interlayer insulating film contacts an upper surface of the silicon semiconductor layer and a lower surface of the first gate electrode.

13. The semiconductor device of claim 1 , further comprising a fourth insulating film formed of a silicon nitride, positioned above the third insulating film, and having a water vapor barrier property.

14. The semiconductor device of claim 1 , wherein the metal oxide semiconductor layer contacts an upper surface of the block layer.

15. A semiconductor device comprising:

an insulating substrate;

a metal oxide semiconductor layer positioned above the insulating substrate;

a first insulating film formed of a silicon nitride and positioned above the insulating substrate;

a block layer positioned between the first insulating film and the metal oxide semiconductor layer, hydrogen diffusion of the block layer being lower than that of the first insulating film,

a second insulating film formed of a silicon oxide between the first insulating film and the block layer;

a third insulating film formed of a silicon oxide, positioned above the a metal oxide semiconductor layer, and covering the metal oxide semiconductor layer;

an interlayer insulating film formed of a silicon oxide between the first insulating film and the insulating substrate; and

a first gate electrode located between the first insulating film and the interlayer insulating film, and facing the metal oxide semiconductor layer via the first insulating film and the second insulating film, wherein

the second insulating film contacts a lower surface of the block layer, and

the third insulating film is formed thicker than the first insulating film, the second insulating film, and the interlayer insulating film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
Priority Claims (1)
JP 2016-006123 · Jan 15, 2016 · national
Continuity (2)
Continuation 15405511 · Jan 13, 2017
Related Publication 20190041932A1 · Feb 7, 2019
Cited By (1)
US 12,543,440