IP Library Granted Patent US 10,685,974
Granted Patent B2
US 10,685,974 · App. 16/132,169 · Granted Jun 16, 2020

Stacked type semiconductor memory device

Inventor: Kotaro Noda (Yokkaichi, JP)
Assignee: Toshiba Memory Corporation
H01L27/11582H01L27/1157
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,685,974
App. No.
16/132,169
Granted
Jun 16, 2020
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.

Claims (17)

1. A method for manufacturing a semiconductor memory device, comprising:

forming a first stacked body including a first insulating film and a first electrode film alternately stacked, forming a first memory hole penetrating the first stacked body in a stacking direction of the first stacked body and forming a filling film within the first memory hole to thereby form a first structure member, the first electrode film functioning as a word line;

stacking a second insulating film and a second electrode film on the first structure member to thereby form a second stacked body, the second electrode film functioning as a selection gate electrode;

forming, on a side of the first memory hole, a slit extending in the first stacked body and the second stacked body in the stacking direction and a first direction crossing the stacking direction;

filling the slit with an insulating material to thereby form an insulating member, the insulating member having a first maximum portion, the first maximum portion having a maximum width of the insulating member along a second direction crossing the stacking direction and the first direction, the first maximum portion being located between a top end portion of the insulating member and a bottom end portion of the insulating member in the stacking direction, the maximum width being greater than a width of the top end portion and a width of the bottom end portion;

forming, immediately above the first memory hole and on a side of the slit, a second memory hole penetrating the second stacked body in the stacking direction; and

removing the filling film within the first memory hole, forming a memory film on a side surface of the first memory hole and the second memory hole and forming a semiconductor pillar within the first memory hole and the second memory hole, the semiconductor pillar having a second maximum portion, the second maximum portion having a maximum diameter of the semiconductor pillar along a plane parallel with the first direction and the second direction, the first maximum portion and the second maximum portion being provided in different positions in the stacking direction.

2. The method according to claim 1 ,

wherein the forming the first structure member is repeated a plurality of times.

3. The method according to claim 1 ,

wherein the forming the first structure member is repeated a plurality of times.

4. The method according to claim 1 , further comprising:

forming a metal film within the slit; and

making the metal film react with the first electrode film to form a silicide,

wherein the first electrode film contains silicon.

5. The method according to claim 1 ,

wherein the first electrode film and the second electrode film include silicon and boron.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
Continuity (4)
Continuation 15629193 · Jun 21, 2017
Continuation 14645672 · Mar 12, 2015
Provisional Application 62047835 · Sep 9, 2014
Related Publication 20190013331A1 · Jan 10, 2019