IP Library › Granted Patent US 10,797,082
Granted Patent B2
US 10,797,082 · App. 16/132,509 · Granted Oct 6, 2020

Thin film transistor array substrate and method of producing the same

Inventors: Tetsuo Kikuchi (Sakai, JP); Tohru Daitoh (Sakai, JP); Hajime Imai (Sakai, JP); Masahiko Suzuki (Sakai, JP); Setsuji Nishimiya (Sakai, JP); Teruyuki Ueda (Sakai, JP); Kengo Hara (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
H01L27/1225G02F1/13338G02F1/13452G02F1/134309G02F1/136286G06F3/044G06F3/0412H01L27/124H01L27/127H01L27/1248H01L27/1288H01L29/45G02F2201/121G02F2201/123
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Quick Facts
Patent No.
US 10,797,082
App. No.
16/132,509
Granted
Oct 6, 2020
Kind
B2
Abstract

A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.

Claims (17)

1. A thin film transistor array substrate including thin film transistors, the thin film transistor array substrate comprising:

gate electrodes of the thin film transistors, the gate electrodes being made from a first metal film;

a first insulating film on the first metal film;

channels of the thin film transistors, the channels being made from a semiconductor film on the first insulating film and overlapping the gate electrodes;

source electrodes of the thin film transistors, the source electrodes being made from a second metal film on the semiconductor film and connected to first ends of the channels;

drain electrodes of the thin film transistors, the drain electrodes being made from the second metal film and connected to second ends of the channels;

pixel electrodes including portions of the semiconductor film having reduced resistances and being connected to the drain electrodes;

a second insulating film on the semiconductor film and the second metal film and including first sections overlapping the pixel electrodes without openings and second sections filling gaps between the source electrodes and the drain electrodes of adjacent thin film transistors, the second sections including bottom surfaces directly contacting top surfaces of the channels; and

a common electrode constructed from a transparent electrode film on the second insulating film and overlapping at least the pixel electrodes.

2. The thin film transistor array substrate according to claim 1 , wherein

the semiconductor film is an oxide semiconductor film,

the second metal film includes metal layers, and

one of the metal layers in contact with the oxide semiconductor film contains at least one of molybdenum and indium zinc oxide.

3. The thin film transistor array substrate according to claim 1 , wherein the common electrode includes position detection electrodes that define a capacitor with a position inputting member to detect a position of input by the position inputting member.

4. The thin film transistor array substrate according to claim 1 , wherein

the semiconductor film includes first sections overlapping the drain electrodes and second sections between the first sections of the semiconductor film and the pixel electrodes, and

the second sections of the semiconductor film have resistances greater than resistances of the pixel electrodes but less than resistances of the channels.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2018
From: KIKUCHI, TETSUO; DAITOH, TOHRU; IMAI, HAJIME; SUZUKI, MASAHIKO; NISHIMIYA, SETSUJI; UEDA, TERUYUKI; HARA, KENGO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 046886/0129 →
Priority Claims (1)
JP 2017-191556 · Sep 29, 2017 · national
Continuity (1)
Related Publication 20190103421A1 · Apr 4, 2019