IP Library Granted Patent US 10,615,127
Granted Patent B2
US 10,615,127 · App. 16/133,178 · Granted Apr 7, 2020

Thinned semiconductor wafer

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Quick Facts
Patent No.
US 10,615,127
App. No.
16/133,178
Granted
Apr 7, 2020
Kind
B2
Abstract

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

Claims (34)

1. A semiconductor wafer including a base material, comprising:

an edge support ring of the base material having a first thickness and an asymmetric width around the semiconductor wafer;

an alignment notch formed on a side surface of edge support ring; and

an interior region of the base material having only a second thickness less than the first thickness,

wherein a wafer scribe mark is disposed on and within a first surface of the edge support ring and aligned to the alignment notch.

2. The semiconductor wafer of claim 1 , wherein the wafer scribe mark is an identification mark.

3. The semiconductor wafer of claim 1 , wherein the second thickness of the base material is less than 75 micrometers.

4. The semiconductor wafer of claim 1 , wherein the second thickness of the base material is 10-50 micrometers.

5. The semiconductor wafer of claim 1 , wherein a width of the semiconductor wafer is 150-300 millimeters.

6. The semiconductor wafer of claim 1 , wherein the interior region of the base material is offset from the wafer scribe mark.

7. The semiconductor wafer of claim 1 , wherein a width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

8. The semiconductor wafer of claim 1 , wherein the asymmetric width of the edge support ring is 3.0-5.0 millimeters to encompass the wafer scribe mark and 2.0-4.2 millimeters elsewhere around the semiconductor wafer.

9. A semiconductor wafer including a base material, comprising:

an edge support ring of the base material having a first thickness and an asymmetric width around the semiconductor wafer;

an alignment notch formed on a side surface of the edge support ring; and

an interior region of a second surface of the base material with only a second thickness less than the first thickness,

wherein a wafer scribe mark is formed on and comprised within a first surface of the edge support ring and aligned to the alignment notch; and

wherein the first thickness of the edge support ring is uniform around the semiconductor wafer.

10. The semiconductor wafer of claim 9 , wherein the wafer scribe mark is an identification mark.

11. The semiconductor wafer of claim 9 , wherein the second thickness of the base material is less than 75 micrometers.

12. The semiconductor wafer of claim 9 , wherein the second thickness of the base material is 10-50 micrometers.

13. The semiconductor wafer of claim 9 , wherein a width of the semiconductor wafer is 150-300 millimeters.

14. The semiconductor wafer of claim 9 , wherein the interior region of the base material is offset from the wafer scribe mark.

15. The semiconductor wafer of claim 9 , wherein a width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

16. The semiconductor wafer of claim 9 , wherein the asymmetric width of the edge support ring is 3.0-5.0 millimeters to encompass the wafer scribe mark and 2.0-4.2 millimeters elsewhere around the semiconductor wafer.

17. A semiconductor wafer including a base material, comprising:

an edge support ring of the base material having a first thickness and an asymmetric width around the semiconductor wafer;

an alignment notch formed on a side surface of the edge support ring; and

an interior region of the base material with only a second thickness less than the first thickness,

wherein a wafer scribe mark is formed on and comprised within a first surface of the edge support ring and aligned to the alignment notch; and

wherein there is no lip on an inner surface of the edge support ring.

18. The semiconductor wafer of claim 17 , wherein the wafer scribe mark is an identification mark.

19. The semiconductor wafer of claim 17 , wherein the interior region of the base material is offset from the wafer scribe mark.

20. The semiconductor wafer of claim 17 , wherein a width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047399, FRAME 0631 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064078/0001 →
SECURITY INTEREST Recorded Nov 1, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047399/0631 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2018
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 046891/0514 →