Control circuit, memory device including the same, and method
A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.
1. A memory device comprising:
a plurality of memories;
a plurality of form factors related to access units of the plurality of memories; and
a control circuit configured to control data from a memory according to an operation cycle that is different from another memory whose form factor is different from that of the memory,
wherein the access units indicate a size of data that the plurality of memories access at a time.
2. The memory device of claim 1 , wherein an access unit of the memory has a burst length that is different from an access unit of the another memory.
3. The memory device of claim 1 , wherein the control circuit configured to generate an internal command based on the access units.
4. The memory device of claim 1 , wherein the control circuit comprising a storage circuit configured to store information about the access units.
5. The memory device of claim 1 , wherein the control circuit comprising an error correction circuit configure to generate an error correction information and perform error correction on a read data read from a memory.
6. A memory device comprising:
a plurality of memories;
a plurality of form factors related to access units of the plurality of memories;
a control circuit configured to manage data according to an operation cycles of a memory whose form factor is different from another memory; and
a storage circuit configured to store information about the access units,
wherein the access units indicate a size of data that the plurality of memories access at a time.
7. The memory device of claim 6 , wherein an access unit of the memory has a burst length that is different from an another access unit of the another memory.
8. The memory device of claim 6 , wherein the control circuit configured to generate an internal command based on the access units.
9. The memory device of claim 6 , wherein the control circuit comprising an access unit comparison circuit configured to compare a size of the data with the access units.
10. The memory device of claim 6 , wherein the control circuit comprising an error correction circuit configure to generate an error correction information and perform error correction on a read data read from a memory.
11. A memory device comprising:
a plurality of memories;
a plurality of form factors related to access units of the plurality of memories;
a control circuit configured to control data from a memory according to an operation cycle that is different from another memory; and
a storage circuit configured to store information about the access units,
wherein the access units indicate a size of data that the plurality of memories access at a time.
12. The memory device of claim 11 , wherein an access unit of the memory has a burst length that is different from an another access unit of the another memory.
13. The memory device of claim 11 , wherein the control circuit configured to generate an internal command based on the access units.
14. The memory device of claim 11 ,
wherein the control circuit comprising an access unit comparison circuit configured to compare a size of the data with the access units.
15. The memory device of claim 11 , wherein the control circuit comprising an error correction circuit configure to generate an error correction information and perform error correction on a read data read from a memory.
16. A memory device comprising:
a plurality of memories;
a plurality of form factors related to access units of the plurality of memories;
a control circuit configured to control data from a memory according to an operation cycle that is different from another memory whose form factor is different from that of the memory; and
a storage circuit configured to store information about the access units,
wherein the access units indicate a size of data that the plurality of memories access at a time.
17. The memory device of claim 16 , wherein an access unit of the memory has a burst length that is different from an another access unit of the another memory.
18. The memory device of claim 16 , wherein the control circuit configured to generate an internal command based on the access units.
19. The memory device of claim 16 , wherein the control circuit comprising an access unit comparison circuit configured to compare a size of the data with the access units.
20. The memory device of claim 16 , wherein the control circuit comprising an error correction circuit configure to generate an error correction information and perform error correction on a read data read from a memory.