IP Library Granted Patent US 10,497,717
Granted Patent B2
US 10,497,717 · App. 16/138,619 · Granted Dec 3, 2019

Semiconductor memory device and method for manufacturing the same

Inventors: Yoshiaki Fukuzumi (Yokkaichi, JP); Shinya Arai (Yokkaichi, JP); Masaki Tsuji (Yokkaichi, JP); Hideaki Aochi (Yokkaichi, JP); Hiroyasu Tanaka (Yokkaichi, JP)
Assignee: Toshiba Memory Corporation
H01L27/11582H01L27/11565H01L27/11575H01L29/42344H01L29/66833H01L29/7926
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Quick Facts
Patent No.
US 10,497,717
App. No.
16/138,619
Granted
Dec 3, 2019
Kind
B2
Abstract

A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Claims (37)

1. A semiconductor memory device comprising:

a connecting member including a semiconductor material;

a first insulating film provided on the connecting member;

a stacked body provided on the first insulating film, the stacked body including electrode films and second insulating films, each of the electrode films and each of the second insulating films being alternately stacked;

three or more semiconductor pillars arrayed along two or more directions different from one another, extending in a stacking direction of the electrode films and the second insulating films, piercing through the stacked body and the first insulating film, and connected to the connecting member;

a third insulating film provided between the semiconductor pillars and the stacked body, the third insulating film including a charge storage layer provided at least between one of the electrode films and one of the semiconductor pillars;

an interconnection member piercing through the stacked body and the first insulating film, the interconnection member being connected to the connecting member, the interconnection member including metal;

a fourth insulating film provided between the interconnection member and the stacked body;

wherein the interconnection member includes:

a core section including metal; and

a peripheral section covering a lower surface and a side surface of the core section and including a semiconductor material.

2. The device according to claim 1 , wherein

a lower section of the interconnection member includes a semiconductor material;

an upper section of the interconnection member includes metal, and

effective impurity concentration in the lower section of the interconnection member is higher than effective impurity concentration in the connecting member.

3. The device according to claim 1 , wherein

effective impurity concentration in a portion of the connecting member in contact with the interconnection member is higher than effective impurity concentration in a portion of the connecting member in contact with one of the semiconductor pillars.

4. The device according to claim 1 , wherein the peripheral section includes silicide of the metal.

5. The device according to claim 1 , wherein the semiconductor pillars and the connecting member are integrally formed.

6. The device according to claim 1 , wherein through-holes extending in the stacking direction are formed in the connecting member.

7. The device according to claim 6 , wherein the through-holes are periodically arrayed.

8. The device according to claim 6 , wherein one of the semiconductor pillars overlaps with one of the through-holes as viewed from the stacking direction.

9. The device according to claim 1 , wherein the third insulating film is also provided on a lower surface of one of the semiconductor pillar.

10. The device according to claim 1 , wherein the interconnection member includes a shoulder portion at least at one location in the stacking direction, a side surface of the interconnection member being non-contiguous at the shoulder portion.

11. The device according to claim 1 , wherein the interconnection member includes a flat portion parallel to a plane, the plane including the stacking direction and a first direction crossing the stacking direction.

12. The device according to claim 1 , wherein at least a part of the interconnection member includes the metal, the part being positioned at a same height level in the stacking direction with an uppermost one of the electrode film.

13. A semiconductor memory device comprising:

a connecting member including a semiconductor material;

a first insulating film provided on the connecting member;

a stacked body provided on the first insulating film, the stacked body including electrode films and second insulating films, each of the electrode films and each of the second insulating films being alternately stacked;

three or more semiconductor pillars arrayed along two or more directions different from one another, extending in a stacking direction of the electrode films and the second insulating films, piercing through the stacked body and the first insulating film, and connected to the connecting member;

a third insulating film provided between the semiconductor pillars and the stacked body, the third insulating film including a charge storage layer provided at least between one of the electrode films and one of the semiconductor pillars;

an interconnection member piercing through the stacked body and the first insulating film, the interconnection member being connected to the connecting member; and

a fourth insulating film provided between the interconnection member and the stacked body,

one of the semiconductor pillars being connected to the connecting member via a side surface of the one of the semiconductor pillars;

wherein the interconnection member includes a shoulder portion at least at one location in the stacking direction, a side surface of the interconnection member being non-contiguous at the shoulder portion.

14. The device according to claim 13 , wherein the interconnection member includes a flat portion parallel to a plane, the plane including the stacking direction and a first direction crossing the stacking direction.

Assignments (3)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
Priority Claims (1)
JP 2014-021747 · Feb 6, 2014 · national
Continuity (3)
Continuation 15345790 · Nov 8, 2016
Continuation 14614588 · Feb 5, 2015
Related Publication 20190027494A1 · Jan 24, 2019