Nonvolatile memory device with intermediate switching transistors and programming method

1. A method of programming in a nonvolatile memory device, the method comprising:

providing a memory block comprising a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings connected to a plurality of bit lines, each cell string comprising a plurality of memory cells connected in series and disposed in the vertical direction;

providing a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent sub blocks in the vertical direction; and

selectively activating each of the plurality of intermediate switching transistors based on a program address during a program operation,

wherein selectively activating each of the plurality of intermediate switching transistors includes turning on one or more intermediate switching transistors in a selected cell string and turning off one or more intermediate switching transistors in an unselected cell string adjacent to the selected cell string in a first direction, based on the program address, and

wherein the selected cell string and the unselected cell are connected to a first bit line of the plurality of bit lines.

2. The method of claim 1 , wherein a selected word line corresponding to the program address is included in a sub block below the boundary portion, and

wherein selectively activating each of the plurality of intermediate switching transistors includes:

turning off intermediate switching transistors in unselected cell strings of the memory block other than the unselected cell string adjacent to the selected cell string.

3. The method of claim 1 , wherein a selected word line corresponding to the program address is included in a sub block above the boundary portion, and

wherein selectively activating each of the plurality of intermediate switching transistors includes:

turning off the plurality of intermediate switching transistors regardless of the program address.

4. The method of claim 1 , wherein the plurality of cell strings includes a plurality of string groups each connected to the same bit line, wherein each of the string groups is electrically connected to the same bit line through a respective string selection transistor, the method further comprising:

independently activating the plurality of intermediate switching transistors by units of the string groups based on the program address during the program operation.

5. The method of claim 1 , wherein a selected word line corresponding to the program address is included in a first sub block below the boundary portion, and further comprising:

applying a first pass voltage to unselected word lines included in the first sub block and applying a second pass voltage lower than the first pass voltage to unselected word lines included in a second sub block above the boundary portion while applying a program voltage to the selected word line.

6. The method of claim 1 , wherein a selected word line corresponding to the program address is included in a second sub block above the boundary portion, and further comprising:

applying a pass voltage to unselected word lines included in the second sub block and floating or applying a low voltage lower than the pass voltage to unselected word lines included in a first sub block below the boundary portion while applying a program voltage to the selected word line.

7. The method of claim 1 , wherein a selected word line corresponding to the program address is included in first sub below the boundary portion, and further comprising:

applying the same pass voltage to unselected word lines included in the first sub block and a second sub block above the boundary portion while applying a program voltage to the selected word line.

8. The method of claim 7 , wherein a selected word line corresponding to the program address is included in the second sub block, and further comprising:

applying the same pass voltage to unselected word lines included in the first and second sub blocks while applying the program voltage to the selected word line.

9. The method of claim 1 , wherein the boundary portion includes a lower boundary portion and an upper boundary portion in each cell string,

wherein the plurality of sub blocks includes a first sub block below the lower boundary portion, a second sub block between the lower boundary portion and the upper boundary portion and a third sub block above the upper boundary portion,

wherein the plurality of intermediate switching transistors include a plurality of lower switching transistors disposed in the lower boundary portion and a plurality of upper switching transistors disposed in the upper boundary portion, and

wherein selectively activating each of the plurality of intermediate switching transistors includes:

when a selected word line corresponding to the program address is included in the first sub block,

turning on one or more lower switching transistors and one or more upper switching transistors in a selected cell string, and

turning off lower and upper switching transistors in unselected cell strings.

10. The method of claim 9 , wherein selectively activating each of the plurality of intermediate switching transistors further includes:

when a selected word line corresponding to the program address is included in the second sub block:

in the selected cell string, turning on one or more upper switching transistors and turning off one or more lower switching transistors, and

turning off lower and upper switching transistors in unselected cell strings.

11. The method of claim 9 , wherein selectively activating each of the plurality of intermediate switching transistors further includes:

when a selected word line corresponding to the program address is included in the third sub block, turning off the plurality of lower and upper switching transistors regardless of the program address.

12. A method of programming in a nonvolatile memory device, comprising:

providing a memory block comprising a first sub block below a stopper layer and a second sub block above the stopper layer where the memory block includes a plurality of cell strings connected to a plurality of bit lines, each cell string comprising a plurality of memory cells connected in series and disposed in a vertical direction;

providing a plurality of intermediate switching transistors disposed in the stopper layer;

turning on one or more intermediate switching transistors in a selected cell string in response to a first string selection transistor connected to a first bit line of the plurality of bit lines in the selected cell string being activated during a program operation; and

turning off the one or more intermediate switching transistors in an unselected cell string adjacent to the selected cell string in a first direction in response to a second string selection transistor connected to the first bit line it the unselected cell string being inactivated during the program operation.

13. The method of claim 12 , further comprising:

in response to a selected word line being included in the first sub block, applying a first pass voltage to unselected word lines in the first sub block and applying a second pass voltage equal to or less than the first pass voltage to unselected word lines in the second sub block while applying a program voltage to the selected word line, and

in response to the selected word line being included in the second sub block, floating or applying a low pass voltage less than the second pass voltage to the unselected word lines in the first sub block and applying the first pass voltage to the unselected word lines in the second sub block, while applying the program voltage to the selected word line.

14. The method of claim 12 , further comprising:

in response to a selected word line being included in the first sub block, applying a first pass voltage to unselected word lines in the first sub block and applying a second pass voltage equal to or less than the first pass voltage to unselected word lines in the second sub block, while applying a program voltage to the selected word line, and

in response to the selected word line being included in the second sub block, applying the first pass voltage to the unselected word lines in the first and second sub blocks, while applying the program voltage to the selected word line.

15. A nonvolatile memory device comprising:

a first memory block divided into a plurality of sub blocks and including a plurality of cell strings each comprising a plurality of memory cells connected in series and disposed in a vertical direction;

a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent sub blocks in the first memory block in the vertical direction; and

a control circuit configured to selectively turn on one or more intermediate switching transistors in a selected cell string of the first memory block independently of intermediate switching transistors in unselected cell strings the first memory block based on a program address during a program operation.

16. The nonvolatile memory device of claim 15 , wherein the control circuit is configured such that when a selected word line corresponding to the program address is included in a first sub block below the boundary portion, the control circuit turns on the one or more intermediate switching transistors in the selected cell string and turns off intermediate switching transistors in the unselected cell strings.

17. The nonvolatile memory device of claim 15 , wherein the control circuit is configured such that when a selected word line corresponding to the program address is included in a second sub block above the boundary portion, the control circuit turns off the plurality of intermediate switching transistors.

18. The nonvolatile memory device of claim 16 , further comprising:

an address decoder configured to provide a plurality of voltages to word lines based on the program address,

wherein the control circuit is configured such that when a selected word line corresponding to the program address is included in a first sub block above the boundary portion, the address decoder provides a program voltage to the selected word line, a first pass voltage to unselected word lines included in the first sub block, and a second pass voltage lower than the first pass voltage to or floating unselected word lines included in a second sub block below the boundary portion.

19. The nonvolatile memory device of claim 15 , wherein the plurality of intermediate switching transistors disposed in the boundary portion includes a first set of intermediate switching transistors and a second set of intermediate switching transistors, wherein each intermediate switching transistor of the first set of intermediate switching transistors is disposed adjacent to and is connected to a respective intermediate switching transistor of the second set of intermediate switching transistors in the vertical direction.

20. The nonvolatile memory device of claim 15 , wherein each of the plurality of cell strings includes:

a first memory cell connected to a first word line formed adjacent to the boundary portion, and configured to store a number of bits smaller than a number of bits stored in each memory cell other than the first memory cell.