Semiconductor device

1. A semiconductor device comprising:

a first conductivity-type semiconductor substrate;

a second conductivity-type base region provided at a front surface side inside the semiconductor substrate,

a gate trench portion provided inside the semiconductor substrate and penetrating through the base region from a front surface of the semiconductor substrate, the gate trench portion having a gate conductive portion, and

a dummy trench portion provided inside the semiconductor substrate and penetrating through the base region from the front surface of the semiconductor substrate, the dummy trench portion including an upper dummy conductive portion configured to carry an emitter potential and a lower gate conductive portion positioned below the upper dummy conductive portion and being configured to have a gate potential,

wherein the lower gate conductive portion of the dummy trench portion is electrically connected to the gate conductive portion of the gate trench portion, and

the gate conductive portion and the lower gate conductive portion together surround the upper dummy conductive portion in cross-section in at least one direction.

2. The semiconductor device according to claim 1 , wherein

in the front surface of the semiconductor substrate, a plurality of the gate trench portions and a plurality of the dummy trench portions surround a mesa region provided in a transistor section of the semiconductor device and having the base region.

3. The semiconductor device according to claim 2 , wherein

in the front surface of the semiconductor substrate, each of the plurality of the dummy trench portions has:

a first straight line portion extending in a first direction,

a second straight line portion extending in a second direction, the second direction being orthogonal relative to the first direction, and

an intersecting portion in which the first straight line portion and the second straight line portion intersect with each other.

4. The semiconductor device according to claim 3 , wherein

in the front surface of the semiconductor substrate, a plurality of the mesa regions are provided being arranged side by side linearly in the first direction and the second direction.

5. The semiconductor device according to claim 3 , wherein

in the front surface of the semiconductor substrate, a plurality of the mesa regions are provided in the transistor section of the semiconductor device and each respectively have a base region including:

a first group within the plurality of the mesa regions, in which respective mesa regions are provided being arranged side by side linearly in the first direction,

a second group within the plurality of the mesa regions, in which respective mesa regions are provided being arranged side by side linearly in the first direction, each mesa region of the second group within the plurality of the mesa regions is a closest one of the second group to the first group in the second direction, and each of the second group within the plurality of the mesa regions is provided so as to be shifted from each other by a half period in the first direction with respect to each mesa region of the first group, and

a third group within the plurality of the mesa regions, in which respective mesa regions are provided being arranged side by side linearly in the first direction, each mesa region of the third group within the plurality of the mesa regions is a second closest one of the third group to the first group in the second direction, and each mesa region of the third group within the plurality of the mesa regions is provided being arranged side by side in the second direction with respect to each mesa region of the first group.

6. The semiconductor device according to claim 4 , wherein

the dummy trench portion is provided in direct contact with a side parallel to the first direction of the plurality of the mesa regions on the front surface of the semiconductor substrate, and

the gate trench portion is provided in direct contact with a side parallel to the second direction of the plurality of the mesa regions on the front surface of the semiconductor substrate.

7. The semiconductor device according to claim 1 , further comprising a diode section adjoined to a transistor section of the semiconductor device, wherein

the transistor section comprises a plurality of the dummy trench portions each having a respective one of a plurality of the lower gate conductive portions, and

the diode section comprises a second plurality of the dummy trench portions, each of the second plurality of dummy trench portions having at least one of the plurality of the lower gate conductive portions.

8. The semiconductor device according to claim 3 , wherein

at least one of the plurality of the dummy trench portions does not have the lower gate conductive portion.

9. The semiconductor device according to claim 3 , further comprising a diode section adjoined to a transistor section of the semiconductor device, wherein

in a plurality of the second straight line portions closest to the diode section among a plurality of the dummy trench portions in the transistor section, second straight line portions adjacent to each other in the second direction are coupled to each other, and

a plurality of the second straight line portions which are closest to the diode section do not have the lower gate conductive portion.

10. The semiconductor device according to claim 1 , wherein

the lower gate conductive portion of the dummy trench portion is provided below the base region.

11. The semiconductor device according to claim 1 , wherein the dummy trench portion has:

an upper insulating film provided on a side portion and a bottom portion of the upper dummy conductive portion, and

a lower insulating film provided on a side portion and a bottom portion of the lower gate conductive portion, the lower insulating film being thicker than the upper insulating film.

12. The semiconductor device according to claim 11 , wherein

the semiconductor substrate has a first conductivity-type drift region positioned below the base region,

the upper insulating film of the dummy trench portion is not in contact with the drift region, and

the lower insulating film of the dummy trench portion is in contact with the drift region.