Using a thermoelectric cooler to reduce heat transfer between heat-conducting plates
Embodiments herein relate to systems, apparatuses, processing, and techniques related to a first heat-conducting plate to be thermally coupled to a first heat source, a thermoelectric cooler (TEC) thermally coupled to the first plate, a second heat-conducting plate thermally coupled to the TEC and to be thermally coupled to a second heat source where the TEC is to at least partially thermally isolate the first plate from the second plate to reduce heat transfer from the first plate to the second plate.
1. A heatsink comprising:
a trench in the heatsink, the trench with a first side and a second side opposite the first side;
a first plate area to be thermally coupled to a first heat source, wherein the first plate area includes a portion of the first side of the trench;
a thermoelectric cooler (TEC) thermally coupled to the first plate area;
a second plate area thermally coupled to the TEC and to be thermally coupled to a second heat source, wherein the second plate area includes a portion of the second side of the trench; and
wherein the TEC at least partially thermally isolates the first plate area from the second plate area to reduce heat transfer from the first plate area to the second plate area.
2. The heatsink of claim 1 , wherein the trench extends from a first side of the heatsink to a second side of the heatsink opposite the first side of the heatsink.
3. The heatsink of claim 1 , wherein the TEC, when coupled to an electric power source, is to transfer heat from the second plate area to the first plate area.
4. The heatsink of claim 1 , wherein the first heat source and the second heat source are not directly thermally coupled.
5. The heatsink of claim 1 , wherein the first heat source is at a greater temperature than the second heat source.
6. The heatsink of claim 1 , wherein the first heat source includes a central processor unit (CPU) and wherein the second heat source includes a high-bandwidth memory (HBM) chip.
7. The heatsink of claim 1 , wherein the first plate area and the second plate area are a portion of an integrated heat sink (IHS).
8. The heatsink of claim 1 , further comprising the first heat source and the second heat source.
9. The heatsink of claim 8 , wherein the first plate area coupled to the first heat source further includes a thermal interface material (TIM) disposed between the first plate area and the first heat source; and wherein the second plate area coupled to the second heat source further includes a TIM disposed between the second plate area and the second heat source.
10. The heatsink of claim 1 , wherein the trench is a first trench and wherein the TEC is a first TEC; and further comprising:
a second trench in the heatsink, the second trench with a first side and a second side opposite the first side;
a third plate area to be thermally coupled to the first heat source, wherein the third plate area is a portion of the first side of the second trench;
a second TEC coupled to the third plate area;
a fourth plate area coupled to the second TEC and coupled to a third heat source, wherein the fourth plate area is a portion of the second side of the second trench.
11. The heatsink of claim 1 , wherein the first plate area and the second plate area are substantially in a plane.
12. A package comprising:
a first area of a heatsink thermally coupled to a first chip;
one or more second areas of the heatsink thermally coupled, respectively, to one or more second chips;
one or more TECs coupled to the one or more second areas of the heatsink and to the first heatsink, wherein the one or more TECs are to at least partially thermally isolate the one or more second heatsinks from the first heatsink; and
wherein the one or more TECs are electrically coupled to a power source, the one or more TECs to transfer heat from at least a portion of the one or more second heatsinks to the first heatsink.
13. The package of claim 12 , wherein the first area of the heatsink is not directly coupled to the one or more second areas of the heatsink.
14. The package of claim 12 , wherein the first area of the heatsink is at a greater temperature than at least one of the one or more second areas of the heatsink.
15. The package of claim 12 , further comprising a substrate; and
wherein the first chip and the one or more second chips are coupled with the substrate.
16. The package of claim 12 , wherein the first chip is a processor and at least one of the one or more second chips is a HBM chip.
17. A method comprising:
inserting a TEC into a trench in a heatsink to identify a first heatsink area and a second heatsink area;
thermally coupling a first chip to the first heatsink area;
thermally coupling a second chip to the second heatsink area,
wherein the TEC is to at least partially thermally isolate the first plate area from the second plate area; and
applying electrical power to the TEC to cause heat to flow from the second heatsink area to the first heatsink area.
18. The method of claim 17 , wherein the first chip is a processor and the second chip is a HBM chip; and
wherein the flow of heat from the second area to the first plate area is to limit an operating temperature of the HBM chip.