Dynamically generated code process sandboxing using authenticated pointers

1. A method operational at a processing circuit, comprising:

ascertaining when dynamically generated code is to be executed;

restricting the dynamically generated code to use a first memory region within an unprotected memory space, where the first memory region is distinct from other memory regions used by other processes executed by the processing circuit;

maintaining a first processing stack for the dynamically generated code within the first memory region while the dynamically generated code is being executed, wherein the first processing stack is separate from a general processing stack used by other processes executed by the processing circuit, wherein a stack pointer is switched to the first processing stack when the dynamically generated code is executed and the stack pointer is switched to the general processing stack when the dynamically generated code ends;

triggering a page fault indicator if at least one of a load, store, or branch instruction within the dynamically generated code invokes an address outside the first memory region; and

enforcing all memory access and transfer of control from the first memory region to other memory regions to occur through authenticated pointers while ignoring or disabling all other pointer authentication related instructions.

2. The method of claim 1 , further comprising:

restricting computational instructions used by the dynamically generated code to operate within the first memory region.

3. The method of claim 1 , further comprising:

triggering a page fault indicator if a special or system instruction within the dynamically generated code invokes an address outside the first memory region.

4. The method of claim 1 , wherein restricting the dynamically generated code is performed by at least one of the processing circuit or an operating system kernel operating thereon.

5. The method of claim 1 , wherein return and call instructions comprise an only way to transfer control to the first memory region.

6. The method of claim 1 , wherein the processing circuit is an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) processor.

7. The method of claim 1 , wherein one or more registers define one or more memory ranges that can be utilized by the dynamically generated code.

8. The method of claim 1 , wherein the first memory region is defined from within writable execution memory regions of a memory device coupled to or integrated within the processing circuit.

9. The method of claim 1 , wherein flags in memory page tables are used to mark all memory pages descending from the first memory region.

10. The method of claim 1 , wherein the dynamically generated code is placed in the first memory region immediately upon being generated by the processing circuit.

11. A processing device, comprising:

a memory device;

a processing circuit coupled to the memory device, the processing circuit configured to:

ascertain when dynamically generated code is to be executed;

restrict the dynamically generated code to use a first memory region within an unprotected memory space of the memory device, where the first memory region is distinct from other memory regions used by other processes executed by the processing circuit;

maintain a first processing stack for the dynamically generated code within the first memory region while the dynamically generated code is being executed, wherein the first processing stack is separate from a general processing stack used by other processes executed by the processing circuit, wherein a stack pointer is switched to the first processing stack when the dynamically generated code is executed and the stack pointer is switched to the general processing stack when the dynamically generated code ends;

trigger a page fault indicator if at least one of a load, store, or branch instruction within the dynamically generated code invokes an address outside the first memory region; and

enforce all memory access and transfer of control from the first memory region to other memory regions to occur through authenticated pointers while ignoring or disabling all other pointer authentication related instructions.

12. The processing device of claim 11 , wherein the processing circuit is further configured to:

restrict computational instructions used by the dynamically generated code to operate within the first memory region;

trigger a page fault indicator if a special or system instruction within the dynamically generated code invokes an address outside the first memory region.

13. The processing device of claim 11 , wherein the processing circuit is an Advanced RISC Machines processor.

14. The processing device of claim 11 , wherein the memory device is integrated within the processing circuit.

15. The processing device of claim 11 , wherein the first memory region is defined from within writable execution memory regions of a memory device coupled to or integrated within the processing circuit.

16. The processing device of claim 11 , wherein the dynamically generated code is placed in the first memory region immediately upon being generated by the processing circuit.

17. A non-transitory processor-readable storage medium having one or more instructions that, when executed by at least one processing circuit, cause the at least one processing circuit to:

ascertain when dynamically generated code is to be executed;

restrict the dynamically generated code to use a first memory region within an unprotected memory space, where the first memory region is distinct from other memory regions used by other processes executed by the processing circuit;

maintain a first processing stack for the dynamically generated code within the first memory region while the dynamically generated code is being executed, wherein the first processing stack is separate from a general processing stack used by other processes executed by the processing circuit, wherein a stack pointer is switched to the first processing stack when the dynamically generated code is executed and the stack pointer is switched to the general processing stack when the dynamically generated code ends;

trigger a page fault indicator if at least one of a load, store, or branch instruction within the dynamically generated code invokes an address outside the first memory region; and

enforce all memory access and transfer of control from the first memory region to other memory regions to occur through authenticated pointers while ignoring or disabling all other pointer authentication related instructions.

18. The non-transitory processor-readable storage medium of claim 17 , further having one or more instructions that, when executed by at least one processing circuit, cause the at least one processing circuit to:

restrict computational instructions used by the dynamically generated code to operate within the first memory region.

19. The non-transitory processor-readable storage medium of claim 17 , further having one or more instructions that, when executed by at least one processing circuit, cause the at least one processing circuit to:

trigger a page fault indicator if a special or system instruction within the dynamically generated code invokes an address outside the first memory region.

20. The non-transitory processor-readable storage medium of claim 17 , wherein restricting the dynamically generated code is performed by at least one of the at least one processing circuit or an operating system kernel operating thereon.