Semiconductor apparatus and equipment

1. A semiconductor apparatus comprising a stack of a first chip having a plurality of pixel circuits arranged in a matrix form of J rows and K columns and a second chip having a plurality of electric circuits arranged in a matrix form of T rows and U columns,

wherein each of the plurality of electric circuits has a first part and a second part, and the first part is connected to at least two pixel circuits of the plurality of pixel circuits and the second part, and the first part is configured to sequentially select a pixel circuit from the two pixel circuits to connect to the second part,

wherein the a1-th row and the e1-th column pixel circuit of the plurality of pixel circuits are connected to the electric circuit of the p-th row and the v-th column of the plurality of electric circuits,

wherein the a2-th row and the f1-th column pixel circuit of the plurality of pixel circuits is connected to the electric circuit of the q-th row and the v-th column of the plurality of electric circuits,

wherein the pixel circuit of the a3-th row and the g1-th column of the plurality of pixel circuits is connected to the electric circuit of the r-th row and the v-th column of the plurality of electric circuits,

wherein the pixel circuit of the a4-th row and the h1-th column of the plurality of pixel circuits is connected to the electric circuit of the s-th row and the v-th column of the plurality of electric circuits, and

T<J and U<K, f1 and g1 are integers between e1 and h1, and q and r are integers between p and s.

2. The semiconductor apparatus according to claim 1 ,

wherein the pixel circuit of the b1-th row and the e1-th column of the plurality of pixel circuits is connected to the electric circuit of the p-th row and the v-th column,

wherein the pixel circuit of the b2-th row and the f1-th column of the plurality of pixel circuits is connected to the electric circuit of the q-th row and the v-th column,

wherein the pixel circuit of the b3-th row and the g1-th column of the plurality of pixel circuits is connected to the electric circuit of the r-th row and the v-th column, and

the pixel circuit of the b4-th row and the h1-th column of the plurality of pixel circuits are connected to the electric circuit of the s-th row and the v-th column.

3. The semiconductor apparatus according to claim 1 ,

wherein the pixel circuit of the b1-th row and the e2-th column of the plurality of pixel circuits is connected to the electric circuit of the p-th row and the w-th column of the plurality of electric circuits,

wherein the pixel circuit of the b2-th row and the f2-th column of the plurality of pixel circuits is connected to the electric circuit of the q-th row and the w-th column of the plurality of electric circuits,

wherein the pixel circuit of the b3-th row and the g2-th column of the plurality of pixel circuits is connected to the electric circuit of the r-th row and the w-th column of the plurality of electric circuits,

the pixel circuit of the b4-th row and the h2-th column of the plurality of pixel circuits are connected to the electric circuit of the s-th row and the w-th column of the plurality of electric circuits.

4. The semiconductor apparatus according to claim 3 ,

wherein the pixel circuit of the a1-th row and the e2-th column of the plurality of pixel circuits is connected to the electric circuit of the p-th row and the w-th column,

wherein the pixel circuit of the a2-th row and the f2-th column of the plurality of pixel circuits is connected to the electric circuit of the q-th row and the w-th column,

wherein the pixel circuit of the a3-th row and the g2-th column of the plurality of pixel circuits is connected to the electric circuit of the r-th row and the w-th column, and

wherein the pixel circuit of the a4-th row and the h2-th column of the plurality of pixel circuits is connected to the electric circuit of the s-th row and the w-th column.

5. The semiconductor apparatus according to claim 3 , wherein f2 and g2 are integers between e2 and h2.

6. The semiconductor apparatus according to claim 1 , wherein e1<f1<g1<h1 and p<q<r<s.

7. The semiconductor apparatus according to claim 1 , wherein J≤T×U<J×K/2.

8. The semiconductor apparatus according to claim 3 , wherein a first output for outputting a signal based on a signal generated by the pixel circuit of the a1-th row and the e1-th column from one of the plurality of electric circuits, a second output for outputting a signal based on a signal generated by the pixel circuit of the a1-th row and the e2-th column from one of the plurality of electric circuits, and a third output for outputting a signal based on a signal generated by the pixel circuit of the a2-th row and the e1-th column from one of the plurality of electric circuits are performed in this order.

9. The semiconductor apparatus according to claim 8 , wherein, in parallel with the first output, a signal based on a signal generated by the pixel circuit of the a1-th row and the f1-th column from one of the plurality of electric circuits.

10. The semiconductor apparatus according to claim 1 ,

wherein, in a direction of alignment of rows of the plurality of electric circuits, a first readout circuit is placed between the plurality of electric circuits and a first side of the second chip and receives signals output from two or more electric circuits of the plurality of electric circuits, and

wherein, in the direction of alignment of rows of the plurality of electric circuits, a second readout circuit is placed between the plurality of electric circuits and a second side of the second chip and receives signals output from two or more electric circuits of the plurality of electric circuits.

11. The semiconductor apparatus according to claim 1 ,

wherein the second chip has a width larger than 33 mm in a direction having an alignment of columns of the plurality of electric circuits, and the second chip has an interface circuit,

wherein U is an even number, and the interface circuit is not placed between an electric circuit of the U/2-th column of the plurality of electric circuits and an outside edge of the first chip, or

wherein U is an odd number, and the interface circuit is not placed between an electric circuit of the (U+1)/2-th column of the plurality of electric circuits and an outside edge of the second chip.

12. The semiconductor apparatus according to claim 1 , wherein the second part of each of the plurality of electric circuits includes an analog-digital converter.

13. The semiconductor apparatus according to claim 12 , wherein the analog-digital converter is a successive approximation register analog-digital converter.

14. An equipment comprising the semiconductor apparatus according to claim 1 and further comprising at least some of:

an optical system configured to be focused on the semiconductor apparatus, a control apparatus configured to control the semiconductor apparatus, a processing apparatus configured to process a signal output from the semiconductor apparatus, a machine apparatus configured to be controlled based on information obtained by the semiconductor apparatus, a display apparatus configured to display the information obtained by the semiconductor apparatus, and a memory apparatus configured to store the information obtained by the semiconductor apparatus.

15. The semiconductor apparatus according to claim 2 ,

wherein the pixel circuit of the a1-th row and the e1-th column is a first pixel circuit,

wherein the pixel circuit of the b1-th row and the e1-th column is a second pixel circuit,

the pixel circuit of the a2-th row and the e1-th column is a third pixel circuit,

wherein the pixel circuit of the b2-th row and the e1-th column is a four-th pixel circuit,

the first pixel circuit and the second pixel circuit are connectable to the electric circuit of the p-th row and the v-th column through a first signal line, and

wherein the third pixel circuit and the four-th pixel circuit are connectable to the electric circuit of the p-th row and the v-th column through a second signal line different from the first signal line.

16. The semiconductor apparatus according to claim 15 , wherein the first part of the electric circuit of the p-th row and the v-th column is configured to be capable of switching between a connection between the first signal line and the second part of the electric circuit of the p-th row and the v-th column and a connection between the second signal line and the second part of the electric circuit of the p-th row and the v-th column.

17. The semiconductor apparatus according to claim 16 , wherein each of the plurality of electric circuits has an amplification transistor and a selection transistor, wherein the amplification transistor of the first pixel circuit is connectable to the first signal line through the selection transistor of the first pixel circuit, wherein the amplification transistor of the second pixel circuit is connectable to the first signal line through the selection transistor of the second pixel circuit.

18. The semiconductor apparatus according to claim 1 , wherein the first part of each of the plurality of electric circuits includes a multiplexer.

19. The semiconductor apparatus according to claim 18 , wherein each of the plurality of electric circuits has a third part connected to the second part, and wherein the third part includes a sensing amplifier.

20. A semiconductor apparatus comprising a stack of a first chip having a plurality of pixel circuits arranged in a matrix form of J rows and K columns and a second chip having a plurality of electric circuits arranged in a matrix form of T rows and U columns,

wherein each of the plurality of electric circuits processes signals generated by the plurality of pixel circuits,

the pixel circuit of the a-th row and the e1-th column of the plurality of pixel circuits is connected to the electric circuit of the p-th row and the v-th column of the plurality of electric circuits,

wherein the pixel circuit of the a-th row and the f1-th column of the plurality of pixel circuits is connected to the electric circuit of the q-th row and the v-th column of the plurality of electric circuits, and

wherein the pixel circuit of the a-th row and the g1-th column of the plurality of pixel circuits is connected to the electric circuit of the r-th row and the v-th column of the plurality of electric circuits,

wherein the pixel circuit of the a-th row and the h1-th column of the plurality of pixel circuits is connected to the electric circuit of the s-th row and the v-th column of the plurality of electric circuits,

wherein the pixel circuit of the a-th row and the e2-th column of the plurality of pixel circuits is connected to the electric circuit of the s-th row and the w-th column of the plurality of electric circuits,

wherein the pixel circuit of the a-th row and the f2-th column of the plurality of pixel circuits is connected to the electric circuit of the r-th row and the w-th column of the plurality of electric circuits, and

wherein T<J and U<K, f1 and g1 are integers between e1 and h1, q and r are integers between p and s, and g1<h1<e2<f2.

21. The semiconductor apparatus according to claim 20 , wherein the pixel circuit of the b-th row and the e1-th column of the plurality of pixel circuits is connected to the electric circuit of the p-th row and the v-th column, wherein the pixel circuit of the b-th row and the f1-th column of the plurality of pixel circuits is connected to the electric circuit of the q-th row and the v-th column, wherein the pixel circuit of the b-th row and the g1-th column of the plurality of pixel circuits is connected to the electric circuit of the r-th row and the v-th column, and the pixel circuit of the b4-th row and the h1-th column of the plurality of pixel circuits are connected to the electric circuit of the s-th row and the v-th column.

22. The semiconductor apparatus according to claim 20 ,

wherein the pixel circuit of the a-th row and the h2-th column of the plurality of pixel circuits is connected to the electric circuit of the p-th row and the w-th column of the plurality of electric circuits,

wherein the pixel circuit of the a-th row and the e3-th column of the plurality of pixel circuits is connected to the electric circuit of the p-th row and the x-th column of the plurality of electric circuits,

wherein the pixel circuit of the a-th row and the f3-th column of the plurality of pixel circuits is connected to the electric circuit of the q-th row and the x-th column of the plurality of electric circuits, and

wherein f2<h2<e3<f3 and v<w<x.

23. The semiconductor apparatus according to claim 1 ,

wherein the pixel circuit of the c1-th row and the e1-th column of the plurality of pixel circuits is connected to the electric circuit of the p2-th row and the v-th column of the plurality of electric circuits,

wherein the pixel circuit of the c2-th row and the f1-th column of the plurality of pixel circuits is connected to the q2-th row and the v-th column of the plurality of electric circuits,

wherein the pixel circuit of the c3-th row and the g1-th column of the plurality of pixel circuits is connected to the electric circuit of the r2-th row and the v-th column of the plurality of electric circuits, and

wherein the pixel circuit of the c4-th row and the h1-th column of the plurality of pixel circuits is connected to the electric circuit of the s2-th row and the v-th column of the plurality of electric circuits.

24. The semiconductor apparatus according to claim 20 , wherein e2=h1+1.

25. The semiconductor apparatus according to claim 20 , wherein T=e2−e1.