Precoding mechanism in PCI-express
In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.
1. An apparatus for serial communication, comprising:
a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link; and
a precoder, coupled to the transceiver, to:
receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler; and
in response to the request from the downlink receiver,
precode the scrambled data bits; and
output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.
2. The apparatus of claim 1 , wherein the precoding request is sent from the downlink receiver during back-channel based transmitter equalization.
3. The apparatus of claim 1 , wherein, upon receipt of the precoding request, the transceiver is further to indicate, via a bit in a transmitted training ordered set, that precoding has been turned on.
4. The apparatus of claim 1 , wherein to precode the scrambled data bits includes to XOR each transmitted data bit with another data bit transmitted just before it.
5. The apparatus of claim 1 , further comprising the scrambler to scramble the subset of the data bits to be transmitted to generate the scrambled data bits.
6. The apparatus of claim 1 , wherein the transceiver transmits the precoded scrambled bits and the other unscrambled bits in a 128:2 ratio.
7. The apparatus of claim 1 , wherein the serial communication link comprises multiple lanes connecting the apparatus and the downlink receiver, and wherein the precoder is further to selectively implement or not implement precoding as to each lane of the serial communication link, in response to either receipt, or no receipt, by the transceiver, as the case may be, of a precoding request from the downlink receiver as to that lane.
8. The apparatus of claim 1 , wherein the precoder, once precoding has been requested for the serial communication link, is to continue to precode the scrambled data bits for that serial communication link, until receipt of a reset signal, from the downlink receiver, by the transceiver.
9. The apparatus of claim 8 , wherein the reset signal is an electric idle exit ordered set (EIEOS) signal.
10. The apparatus of claim 1 , wherein the precoding request indicates that precoding is to begin prior to the transceiver entering a predetermined data rate.
11. The apparatus of claim 1 , wherein the serial communication link is a peripheral component interconnect-express link.
12. A circuit card for computing, comprising:
a transceiver to receive a precoding request from a downlink receiver external to the circuit card, across a peripheral component interconnect-express (PCIe) link; and
a scrambler, to scramble a subset of a plurality of data bits to be transmitted to the downlink receiver over the PCIe link,
wherein the transceiver, in response to the request from the downlink receiver, is to further:
precode the scrambled data bits, and transmit the precoded scrambled data bits to the downlink receiver together with unscrambled data bits.
13. The circuit card of claim 12 , wherein the precoding request is sent from the downlink receiver during back-channel based transmitter equalization.
14. The circuit card claim 12 , wherein the transceiver is further to indicate, via a bit in a transmitted PCIe training ordered set, that precoding has been turned on.
15. The circuit card of claim 12 , wherein to precode the scrambled data bits includes to XOR each transmitted data bit with another bit transmitted just before it.
16. The circuit card of claim 12 , wherein the transceiver transmits the precoded scrambled bits and the other unscrambled bits in a 128:2 ratio.
17. The circuit card of claim 12 , wherein the PCIe link comprises multiple lanes connecting the transceiver and the downlink receiver, and wherein the transceiver is further to selectively implement or not implement precoding as to each lane of the PCIe link, in response to either receipt, or no receipt, by the transceiver, as the case may be, of a precoding request from the downlink receiver as to that lane.
18. The circuit card of claim 12 , wherein the transceiver, once precoding has been requested for the PCIe link, is to continue to precode the scrambled data bits for that PCIe link, until receipt of a reset signal from the downlink receiver by the transceiver.
19. The circuit card of claim 18 , wherein the reset signal is an electric idle exit ordered set (EIEOS) signal.
20. The circuit card of claim 12 , wherein the precoding request indicates that precoding is to begin prior to the transceiver entering a predetermined data rate.
21. A system, comprising:
first circuit component having a downlink receiver to send a precoding request to an uplink transmitter of a second circuit component across a serial communication link during back-channel based transmitter equalization; and
the second circuit component having the uplink transmitter, to receive the precoding request from, and transmit data bits to, the downlink receiver, across the serial communication link,
wherein the transmitter scrambles a subset of data bits to be transmitted, of a pre-defined type, and
wherein, in response to the request from the downlink receiver, the transmitter precodes the scrambled data bits, and transmits them to the downlink receiver, together with other unscrambled data bits, across the serial communication link.
22. The system of claim 21 , wherein the serial communication link comprises multiple lanes connecting the uplink transmitter and the downlink receiver, and wherein the uplink transmitter is further to selectively implement or not implement precoding as to each lane of the serial communication link, in response to either receipt, or no receipt, by the uplink transmitter, as the case may be, of a precoding request from the downlink receiver as to that lane.
23. The system of claim 22 , wherein the downlink receiver makes a request for precoding as to a lane, or as to the entire link, based, at least in part, on its decision feedback equalization setup.
24. The system of claim 21 , wherein to precode the scrambled data bits includes to XOR each transmitted data bit with another data bit transmitted just before it.
25. The system of claim 21 , wherein the precoding request indicates that the uplink transmitter is to begin precoding prior to transmitting at a predetermined data rate.