CMOS anti-fuse cell
A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a drain P+ diffusion deposited in the N-well, a source P+ diffusion deposited in the N-well, and an oxide layer deposited on the N-well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
1. An apparatus, comprising:
a P-well; and
an anti-fuse cell formed on the P-well and comprising:
an oxide layer deposited on the P-well;
a control gate deposited on the oxide layer; and
a drain N+ diffusion deposited in the P-well and below an overlapping region of the oxide layer, and wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain N+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path through the oxide layer that is confined to occur in the overlapping region.
2. The apparatus of claim 1 , wherein the anti-fuse cell forms an NMOS transistor.
3. The apparatus of claim 1 , wherein the voltage threshold of the oxide layer is approximately 4 volts.
4. The apparatus of claim 1 , further comprising a second transistor that comprises:
a second drain N+ diffusion deposited in the P-well;
a second oxide layer deposited on the P-well and having end regions that overlap the second drain N+ diffusion and the drain N+ diffusion of the anti-fuse cell; and
a select gate deposited on the second oxide layer.
5. The apparatus of claim 4 , wherein the second drain N+ diffusion is connected to a bit line.
6. The apparatus of claim 1 , further comprising a source N+ diffusion deposited in the P-well and below a second overlapping region of the oxide layer, and wherein a second bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the source N+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path through the oxide layer that is confined to occur in the second overlapping region.
7. A three transistor (3T) anti-fuse apparatus, comprising:
a P-well; and
an anti-fuse cell formed on the P-well and comprising:
an oxide layer deposited on the P-well;
a control gate deposited on the oxide layer;
a drain N+ diffusion deposited in the P-well and below a first overlapping region of the oxide layer; and
a source N+ diffusion deposited in the P-well and below a second overlapping region of the oxide layer;
a first transistor formed on the P-well, wherein the first transistor couples a bit line to the drain N+ diffusion of the anti-fuse cell;
a second transistor formed on the P-well, wherein the second transistor couples the bit line to the source N+ diffusion of the anti-fuse cell; and
wherein the oxide layer has a first leakage path confined to occur in the first overlapping region when the anti-fuse cell is programed with a first bit, and wherein the oxide layer has a second leakage path confined to occur in the second overlapping region when the anti-fuse cell is programed with a second bit.
8. The apparatus of claim 7 , wherein the first bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain N+ diffusion exceeds a voltage threshold of the oxide layer.
9. The apparatus of claim 7 , wherein the second bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the source N+ diffusion exceeds a voltage threshold of the oxide layer.
10. The apparatus of claim 7 , wherein the first transistor comprises:
a second drain N+ diffusion deposited in the P-well and connected to the bit line;
a second oxide layer deposited on the P-well and having end regions that overlap the second drain N+ diffusion and the drain N+ diffusion of the anti-fuse cell; and
a select gate deposited on the second oxide layer.
11. The apparatus of claim 7 , wherein the second transistor comprises:
a second source N+ diffusion deposited in the P-well and coupled to the bit line;
a second oxide layer deposited on the P-well and having end regions that overlap the second source N+ diffusion and the source N+ diffusion of the anti-fuse cell; and
a select gate deposited on the second oxide layer.
12. A method of operating an anti-fuse cell that comprises an oxide layer deposited on a P-well, a control gate deposited on the oxide layer, and a drain N+ diffusion deposited in the P-well and below an overlapping region of the oxide layer, and wherein a bit of the anti-fuse cell is programmed when a leakage path is formed through the oxide layer that is confined to occur in the overlapping region, the method comprising:
applying a first voltage to the control gate;
applying a second voltage to the drain N+ diffusion, wherein the first voltage is lower than the second voltage;
reading current flow through the leakage path if the anti-fuse cell is programmed to be an on-cell; and
reading no current to flow through the leakage path if the anti-fuse cell is programmed to be an off-cell.
13. The method of claim 12 , further comprising an operation of applying zero volts to the P-well.
14. The method of claim 12 , wherein the first voltage is zero volts and the second voltage is one volt.
15. The method of claim 12 , wherein the operation of applying the first voltage to the control gate turns off a channel region of the anti-fuse cell.
16. A method of operating an anti-fuse cell that comprises an oxide layer deposited on a N-well, a control gate deposited on the oxide layer, and a drain P+ diffusion deposited in the N-well and below an overlapping region of the oxide layer, and wherein a bit of the anti-fuse cell is programmed when a leakage path is formed through the oxide layer that is confined to occur in the overlapping region, the method comprising:
applying a first voltage to the control gate;
applying a second voltage to the drain P+ diffusion, wherein the first voltage is higher than the second voltage;
reading current flow through the leakage path if the anti-fuse cell is programmed to be an on-cell; and
reading no current to flow through the leakage path if the anti-fuse cell is programmed to be an off-cell.
17. The method of claim 16 , further comprising an operation of applying a VDD supply voltage to the N-well.
18. The method of claim 17 , wherein the VDD supply voltage is three volts.
19. The method of claim 16 , wherein the first voltage is three volts and the second voltage is one volt.
20. The method of claim 16 , wherein the operation of applying the first voltage to the control gate turns off a channel region of the anti-fuse cell.
21. A method of operating an three transistor (3T) anti-fuse cell that comprises an oxide layer deposited on a P-well, a control gate deposited on the oxide layer, a drain N+ diffusion deposited in the P-well and below a first overlapping region of the oxide layer, and a source N+ diffusion deposited in the P-well and below a second overlapping region of the oxide layer, wherein a first transistor couples a bit line to the drain N+ region and a second transistor couples the bit line to the source N+ region, wherein the oxide layer has a first leakage path confined to occur in the first overlapping region when the anti-fuse cell is programed with a first bit, and wherein the oxide layer has a second leakage path confined to occur in the second overlapping region when the anti-fuse cell is programed with a second bit, the method comprising:
applying a first voltage to the control gate;
turning on the first transistor to couple the bit line to the drain N+ diffusion;
applying a second voltage through the first transistor to the drain N+ diffusion, wherein the first voltage is lower than the second voltage;
reading current flow from the control gate through the first leakage path to the bit line, if the anti-fuse cell is programmed to be an on-cell; and
reading no current to flow from the control gate through the first leakage path to the bit line if the anti-fuse cell is programmed to be an off-cell.
22. The method of claim 21 , further comprising:
turning on the second transistor to couple the bit line to the source N+ diffusion;
applying a third voltage through the second transistor to the source N+ diffusion, wherein the first voltage is lower than the third voltage;
reading current flow from the control gate through the second leakage path to the bit line, if the anti-fuse cell is programmed to be an on-cell; and
reading no current to flow from the control gate through the second leakage path to the bit line if the anti-fuse cell is programmed to be an off-cell.
23. The method of claim 22 , further comprising an operation of applying zero volts to the P-well.
24. The method of claim 22 , wherein the first voltage is zero volts, the second voltage is one volt and the third voltage is one volt.
25. The method of claim 22 , wherein the operation of applying the first voltage to the control gate turns off a channel region of the anti-fuse cell.