Methods and apparatus to emulate graphics processing unit instructions
Embodiments are disclosed for emulation of graphics processing unit instructions. An example apparatus includes a kernel accessor to access an instruction of an original GPU kernel, the original GPU kernel intended to be executed at a first GPU. An instruction support determiner is to determine whether execution of the instruction is supported by a second GPU different from the first GPU. An instruction modifier is to, in response to determining that the execution of the instruction is not supported by the second GPU, create an instrumented GPU kernel based on the original GPU kernel. The instrumented GPU kernel includes an emulation sequence. The emulation sequence is to, when executed by the second GPU, cause the second GPU to emulate execution of the instruction by the first GPU.
1. An apparatus to create instrumented graphics processing unit (GPU) kernels, the apparatus comprising:
a kernel accessor to access an instruction of an original GPU kernel, the original GPU kernel intended to be executed at a first GPU;
an instruction support determiner to determine whether execution of the instruction is supported by a second GPU different from the first GPU; and
an instruction modifier to, in response to determining that the execution of the instruction is not supported by the second GPU, create an instrumented GPU kernel based on the original GPU kernel, the instrumented GPU kernel including an emulation sequence, the emulation sequence to, when executed by the second GPU, cause the second GPU to emulate execution of the instruction by the first GPU.
2. The apparatus of claim 1 , wherein the creating of the GPU kernel includes performing an in-line replacement of the instruction of the original GPU kernel with the emulation sequence.
3. The apparatus of claim 1 , wherein the instruction modifier is to replace the instruction with a first jump instruction, and append the emulation sequence and a second jump instruction to the instrumented GPU kernel.
4. The apparatus of claim 3 , wherein the first jump instruction is to, when executed by the second GPU, cause the second GPU to execute the emulation sequence, and the second jump instruction is to, when executed by the second GPU, cause the second GPU to execute an emulation cleanup instruction.
5. The apparatus of claim 1 , further including a compiler to compile a high-level instruction to create the emulation sequence.
6. The apparatus of claim 1 , further including:
an instruction offloading communicator to monitor a shared memory for an emulation offloading request from the second GPU; and
an instruction offloading executor to, in response to detection of the emulation offloading request, emulate execution of the instruction by the first GPU, the instruction offloading communicator is further to provide a result of the emulation to the second GPU via the shared memory.
7. At least one non-transitory computer readable medium comprising instructions that, when executed, cause at least one processor to at least:
access an instruction of an original GPU kernel, the original GPU kernel intended to be executed at a first GPU;
determine whether execution of the instruction is supported by a second GPU different from the first GPU; and
in response to a determination that the execution of the instruction is not supported by the second GPU, create an instrumented GPU kernel based on the original GPU kernel, the instrumented GPU kernel including an emulation sequence, the emulation sequence to, when executed by the second GPU, cause the second GPU to emulate execution of the instruction by the first GPU.
8. The at least one non-transitory computer readable medium of claim 7 , wherein the instructions, when executed, cause the at least one processor to create the GPU kernel by performing an in-line replacement of the instruction of the original GPU kernel with the emulation sequence.
9. The at least one non-transitory computer readable medium of claim 7 , wherein the instructions, when executed, cause the at least one processor to:
replace the instruction of the original GPU kernel with a first jump instruction; and
append the emulation sequence and a second jump instruction to the instrumented GPU kernel.
10. The at least one non-transitory computer readable medium of claim 9 , wherein the first jump instruction is to, when executed by the second GPU, cause the second GPU to execute the emulation sequence, and the second jump instruction is to, when executed by the second GPU, cause the second GPU to execute an emulation cleanup instruction.
11. The at least one non-transitory computer readable medium of claim 7 , wherein the instructions, when executed, cause the at least one processor to compile a high-level instruction to create the emulation sequence.
12. The at least one non-transitory computer readable medium of claim 7 , wherein the instructions, when executed, cause the at least one processor to:
monitor a shared memory for an emulation offloading request from the second GPU;
in response to detection of the emulation offloading request, emulate, by executing an instruction with the processor, execution of the instruction by the first GPU; and
provide a result of the emulation to the second GPU via the shared memory.
13. An apparatus to create instrumented graphics processing unit (GPU) kernels, the apparatus comprising:
means for accessing an instruction of an original GPU kernel, the original GPU kernel intended to be executed at a first GPU;
means for determining whether execution of the instruction is supported by a second GPU different from the first GPU; and
means for modifying to, in response to a determination that the execution of the instruction is not supported by the second GPU, create an instrumented GPU kernel based on the original GPU kernel, the instrumented GPU kernel including an emulation sequence, the emulation sequence to, when executed by the second GPU, cause the second GPU to emulate execution of the instruction by the first GPU.
14. The apparatus of claim 13 , wherein the means for modifying is to perform an in-line replacement of the instruction of the original GPU kernel with the emulation sequence.
15. The apparatus of claim 13 , wherein the means for modifying is to replace the instruction with a first jump instruction, the means for modifying to append the emulation sequence and a second jump instruction to the instrumented GPU kernel.
16. The apparatus of claim 15 , wherein the first jump instruction is to, when executed by the second GPU, cause the second GPU to execute the emulation sequence, and the second jump instruction is to, when executed by the second GPU, cause the second GPU to execute an emulation cleanup instruction.
17. The apparatus of claim 13 , further including means for compiling a high-level instruction to create the emulation sequence.
18. The apparatus of claim 13 , further including:
means for monitoring a shared memory for an emulation offloading request from the second GPU; and
means for emulating, in response to detection of the emulation offloading request, execution of the instruction by the first GPU, the means for monitoring to provide a result of the emulation to the second GPU via the shared memory.
19. A method for creating instrumented graphics processing unit (GPU) kernels, the method comprising:
accessing an instruction of an original GPU kernel, the original GPU kernel to be executed at a first GPU;
determining, by executing an instruction with a processor, whether execution of the instruction is supported by a second GPU different from the first GPU; and
in response to determining that the execution of the instruction is not supported by the second GPU, creating an instrumented GPU kernel based on the original GPU kernel, the instrumented GPU kernel including an emulation sequence, the emulation sequence to, when executed by the second GPU, cause the second GPU to emulate execution of the instruction by the first GPU.
20. The method of claim 19 , wherein the creating of the GPU kernel includes performing an in-line replacement of the instruction of the original GPU kernel with the emulation sequence.
21. The method of claim 19 , wherein the creating of the instrumented GPU kernel includes:
replacing the instruction of the original GPU kernel with a first jump instruction; and
appending the emulation sequence and a second jump instruction to the instrumented GPU kernel.
22. The method of claim 21 , wherein the first jump instruction is to, when executed by the second GPU, cause the second GPU to execute the emulation sequence, and the second jump instruction is to, when executed by the second GPU, cause the second GPU to execute an emulation cleanup instruction.
23. The method of claim 19 , further including compiling a high-level instruction to create the emulation sequence.
24. The method of claim 19 , further including:
monitoring a shared memory for an emulation offloading request from the second GPU;
in response to detection of the emulation offloading request, emulating, by executing an instruction with the processor, execution of the instruction by the first GPU; and
providing a result of the emulation to the second GPU via the shared memory.