Fan-out wafer level packaging of semiconductor devices
In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.
1. A method of producing a fan-out wafer level package (FOWLP) semiconductor device, the method comprising:
separating a semiconductor wafer into a plurality of semiconductor die, a semiconductor die of the plurality of semiconductor die including:
an active surface;
a backside surface, opposite the active surface;
a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface;
a plurality of conductive bumps disposed on the active surface; and
an insulating layer disposed on a first portion of the active surface, the first portion of the active surface being disposed between the plurality of conductive bumps;
increasing spacing between the plurality of semiconductor die;
encapsulating, in a molding compound, the backside surface, and the plurality of side surfaces;
partially encapsulating, in the molding compound, a second portion of the active surface, the second portion of the active surface being disposed adjacent to the first portion of the active surface and between the plurality of conductive bumps and a perimeter edge of the active surface, the molding compound also being disposed between the plurality of semiconductor die, the first portion of the active surface excluding the molding compound; and
forming a signal distribution structure, the signal distribution structure being disposed on the plurality of conductive bumps, the insulating layer and the molding compound, the signal distribution structure being configured to provide respective electrical connections to the plurality of conductive bumps.
2. The method of claim 1 , further comprising forming a channel through the molding compound to singulate the FOWLP semiconductor device including the semiconductor die.
3. The method of claim 1 , further comprising:
prior to separating the semiconductor wafer into the plurality of semiconductor die, disposing the semiconductor wafer on a first carrier,
wherein the increasing spacing between the plurality of semiconductor die includes, after cutting the semiconductor wafer into the plurality of semiconductor die:
picking the plurality of semiconductor die off the first carrier; and
placing the plurality of semiconductor die on a second carrier with the increased spacing.
4. The method of claim 1 , further comprising:
prior to separating the semiconductor wafer into the plurality of semiconductor die, disposing the semiconductor wafer on a first carrier tape,
wherein the increasing spacing between the plurality of semiconductor die includes, after cutting the semiconductor wafer into the plurality of semiconductor die, stretching the first carrier tape along a first axis of the first carrier tape and along a second axis of the first carrier tape.
5. The method of claim 4 , wherein increasing the spacing between the plurality of semiconductor die further includes:
after stretching the first carrier tape, transferring the plurality of semiconductor die from the first carrier tape to a second carrier tape; and
stretching the second carrier tape along a first axis of the second carrier tape, and along a second axis of the second carrier tape.
6. The method of claim 5 , wherein transferring the plurality of semiconductor die from the first carrier tape to the second carrier tape includes flip transferring the plurality of semiconductor die from the first carrier tape to the second carrier tape.
7. The method of claim 1 , wherein forming the signal distribution structure includes:
forming a first dielectric layer on the insulating layer, the plurality of conductive bumps and the molding compound, the first dielectric layer having a planar surface;
forming a plurality of via openings through the first dielectric layer; and
forming a plurality of electrical connections to the plurality of conductive bumps, each of the plurality of electrical connections being disposed on the planar surface of the first dielectric layer and disposed in a respective via opening of the plurality of via openings.
8. The method of claim 7 , wherein:
the plurality of conductive bumps is a first plurality of conductive bumps, and
forming the signal distribution structure further includes:
forming a second dielectric layer disposed on the plurality of electrical connections and the first dielectric layer;
forming a second plurality of via openings through the second dielectric layer;
and
forming a second plurality of conductive bumps that are disposed in respective via openings of the second plurality of via openings in the second dielectric layer, and disposed on respective electrical connections of the plurality of electrical connections.
9. A method of producing a fan-out wafer level package (FOWLP) semiconductor device, the method comprising:
disposing a semiconductor wafer on a first carrier tape;
separating the semiconductor wafer into a plurality of semiconductor die, a semiconductor die of the plurality of semiconductor die including:
an active surface;
a backside surface, opposite the active surface;
a plurality of side surfaces each extending between the active surface and the backside surface;
a plurality of conductive bumps disposed on the active surface; and
an insulating layer disposed on a first portion of the active surface, the first portion of the active surface being disposed between the plurality of conductive bumps;
increasing spacing between the plurality of semiconductor die by:
stretching the first carrier tape along a first axis of the first carrier tape and along a second axis of the first carrier tape;
after stretching the first carrier tape, transferring the plurality of semiconductor die from the first carrier tape to a second carrier tape; and
stretching the second carrier tape along a first axis of the second carrier tape and along a second axis of the second carrier tape;
encapsulating, in a molding compound, the backside surface, and the plurality of side surfaces;
partially encapsulating, in the molding compound, a second portion of the active surface, the second portion of the active surface being disposed adjacent to the first portion of the active surface and between the plurality of conductive bumps and a perimeter edge of the active surface, the molding compound also being disposed between the plurality of semiconductor die, the first portion of the active surface excluding the molding compound; and
forming a signal distribution structure, the signal distribution structure being disposed on the plurality of conductive bumps, the insulating layer and the molding compound, the signal distribution structure being configured to provide respective electrical connections to the plurality of conductive bumps.
10. The method of claim 9 , wherein forming the signal distribution structure includes:
forming a dielectric layer on the insulating layer, the plurality of conductive bumps and the molding compound, the dielectric layer having a planar surface;
forming a plurality of via openings through the dielectric layer; and
forming a plurality of electrical connections to the plurality of conductive bumps, each of the plurality of electrical connections being disposed on the planar surface of the dielectric layer and disposed in a respective via opening of the plurality of via openings.
11. The method of claim 10 , wherein:
the plurality of conductive bumps is a first plurality of conductive bumps, and
forming the signal distribution structure further includes forming a second plurality of conductive bumps disposed on respective electrical connections of the plurality of electrical connections.
12. The method of claim 9 , further comprising forming a channel through the molding compound to singulate the FOWLP semiconductor device including the semiconductor die.
13. The method of claim 9 , further comprising, prior to cutting the semiconductor wafer into the plurality of semiconductor die:
grinding the backside surface of the semiconductor die to reduce a thickness of the semiconductor die; and
forming a backside metal layer on the backside surface of the semiconductor die.