Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection
A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.
1. A method of forming a semiconductor device, the method comprising:
forming a stack over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate;
removing at least a portion of the bottom sacrificial layer so as to create openings;
forming inner spacers in the openings adjacent to the bottom sacrificial layer;
removing the bottom sacrificial layer so as to create a void;
forming an isolation layer on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate; and
forming source and drain regions overlying both the isolation layer and the air gap having been formed by the isolation layer.
2. The method of claim 1 , wherein removing the portion of the bottom sacrificial layer so as to create the openings comprises recessing sides of the bottom sacrificial layer.
3. The method of claim 2 , wherein recessing the sides of the bottom sacrificial layer causes a width of the bottom sacrificial layer to be less than a width of the stack.
4. The method of claim 1 , wherein the void is between the stack and the substrate.
5. The method of claim 1 , wherein the void is between the inner spacers.
6. The method of claim 1 , wherein the isolation layer and the air gap physically and electrically separate the source and drain regions from the substrate.
7. The method of claim 1 , wherein:
the stack comprises a plurality of channel layers, each of the plurality of channels layers being separate from one another;
a conductive gate structure is formed on the plurality of channel layers; and
the isolation layer separates a bottom portion of the conductive gate structure from the substrate.
8. The method of claim 1 , wherein the isolation layer comprises a nitride.
9. The method of claim 1 , wherein the isolation layer comprises silicon boron carbide nitride.
10. The method of claim 1 , wherein:
source and drain regions are formed on the isolation layer and are operable to permit current flow via channel layers in the stack; and
the isolation layer is positioned to prevent current leakage from one of the source and drain regions to another one of the source and drain regions via the substrate.