Nanosheet with dual isolation regions separated by buried inner spacer
Embodiments of the invention include a transistor comprising a gate region and a source/drain region. A first isolation layer is under the gate region. A second isolation layer is separated from the first isolation layer by a third isolation layer.
1 . A semiconductor structure comprising:
a transistor comprising a gate region and a source/drain region, a first isolation layer being under the gate region; and
a second isolation layer separated from the first isolation layer by a third isolation layer, wherein the second isolation layer is in contact with the source/drain region.
2 . The semiconductor structure of claim 1 , wherein the first isolation layer is under inner spacers that are adjacent to the gate region.
3 . The semiconductor structure of claim 1 , wherein the second isolation layer is under the source/drain region.
4 . The semiconductor structure of claim 1 , wherein the third isolation layer is under the source/drain region.
5 . The semiconductor structure of claim 1 , wherein the third isolation layer comprises inner spacer material and is formed on a sidewall of the first isolation layer, inner spacers being formed adjacent to the source/drain region and comprising the inner spacer material.
6 . The semiconductor structure of claim 1 , wherein the third isolation layer comprises a different width than an inner spacer.
7 . The semiconductor structure of claim 1 , wherein the third isolation layer extends from an inner spacer.
8 . The semiconductor structure of claim 1 , wherein the first and second isolation layers comprise different thicknesses.
9 . The semiconductor structure of claim 1 , wherein the first and second isolation layers comprise different materials.
10 . The semiconductor structure of claim 1 , wherein the third isolation layer is adjacent to the first isolation layer, the second isolation layer, and the source/drain region.
11 . A method comprising;
forming a transistor comprising a gate region and source/drain region, a first isolation layer being under the gate region; and
providing a second isolation layer separated from the first isolation layer by a third isolation layer, wherein the second isolation layer is in contact with the source/drain region.
12 . The method of claim 11 , wherein the first isolation layer is under inner spacers that are adjacent to the gate region.
13 . The method of claim 11 , wherein the second isolation layer is under the source/drain region.
14 . The method of claim 11 , wherein the third isolation layer is under the source/drain region.
15 . The method of claim 11 , wherein the third isolation layer comprises inner spacer material and is formed on a sidewall of the first isolation layer, inner spacers being formed adjacent to the epitaxial region and comprising the inner spacer material.
16 . The method of claim 11 , wherein the third isolation layer comprises a different width than an inner spacer.
17 . The method of claim 11 , wherein the third isolation layer extends from an inner spacer.
18 . The method of claim 11 , wherein the first and second isolation layers comprise different thicknesses.
19 . The method of claim 11 , wherein the first and second isolation layers comprise different materials.
20 . The method of claim 11 , wherein the third isolation layer is adjacent to the first isolation layer, the second isolation layer, and the epitaxial region.
21 . A semiconductor structure comprising:
a transistor comprising a gate region and a source/drain region, a backside contact being adjacent to the source/drain region, wherein inner spacers are adjacent to the gate region; and
an isolation layer under the gate region and separated from the backside contact by another isolation layer, wherein the another isolation layer is under the source/drain region, wherein the another isolation layer is in contact with both a sidewall of the inner spacers and a sidewall of the backside contact.
22 . The semiconductor structure of claim 21 , wherein the isolation layer is under inner spacers that are adjacent to the gate region.
23 . The semiconductor structure of claim 21 , wherein the another isolation layer comprises inner spacer material and is formed on a sidewall of the isolation layer, the inner spacers being formed adjacent to the source/drain region and comprising the inner spacer material.
24 . A method comprising:
forming a transistor comprising a gate region and a source/drain region, a backside contact being adjacent to the source/drain region, wherein inner spacers are adjacent to the gate region; and
providing an isolation layer under the gate region and separated from the backside contact by another isolation layer, wherein the another isolation layer is under the source/drain region, wherein the another isolation layer is in contact with both a sidewall of the inner spacers and a sidewall of the backside contact.