Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate

1. A method of fabricating devices on a substrate, the method comprising:

performing memory fabrication operations to form a non-volatile memory device in a first region of the substrate, wherein the memory fabrication operations include:

forming a first region of a nanosheet stack over the first region of the substrate, wherein the first region of the nanosheet stack comprises nanosheet layers of a first type of semiconductor material alternating with nanosheet layers of a second type of semiconductor material;

replacing a first portion of the first region of the nanosheet stack with a control gate of the non-volatile memory device; and

providing a charge trapping region of the non-volatile memory device under the control gate.

2. The method of claim 1 , wherein the memory fabrication operations further include replacing a second portion of the first region of the nanosheet stack with memory source or drain (S/D) regions.

3. The method of claim 2 , wherein:

a portion of the first region of the substrate is between a first one of the S/D regions and a second one of the S/D regions; and

a channel region comprises the portion of the first region of the substrate that is between the first one of the S/D regions and the second one of the S/D regions.

4. The method of claim 3 , wherein the non-volatile memory device comprises:

a non-volatile memory transistor formed over the first region of the substrate;

the control gate; and

the charge trapping region.

5. The method of claim 4 , wherein the non-volatile memory transistor comprises:

the first one of the S/D regions;

the second one of the S/D regions; and

the channel region.

6. The method of claim 1 , wherein the charge trapping region comprises at least one of the nanosheet layers of the first type of semiconductor material.

7. The method of claim 6 , wherein the charge trapping region further comprises at least one of the nanosheet layers of the second type of semiconductor material.

8. The method of claim 7 , wherein:

the first type of semiconductor material comprises silicon; and

the second type of semiconductor material comprises silicon germanium.

9. The method of claim 1 , wherein:

the memory fabrication operations further include forming a dielectric stack under the control gate; and

the dielectric stack comprises the charge trapping region.

10. The method of claim 9 , wherein the dielectric stack further comprises:

a first dielectric region;

a second dielectric region; and

the charge trapping region between the first dielectric region and the second dielectric region.

11. The method of claim 10 , wherein the memory fabrication operations further include:

prior to forming the first region of the nanosheet stack over the first region of the substrate, forming a first region of a first sacrificial nanosheet over the first region of the substrate such that the first region of the first sacrificial nanosheet is between the first region of the substrate and the first region of the nanosheet stack; and

replacing the first region of the first sacrificial nanosheet with the second dielectric region of the dielectric stack.

12. The method of claim 1 further comprising:

performing nanosheet fabrication operations to form a nanosheet field effect transistor (FET) device in a second region of the substrate, wherein the nanosheet fabrication operations include:

forming a second region of the nanosheet stack over a second region of the substrate, wherein the second region of the nanosheet stack comprises nanosheet layers of the first type of semiconductor material alternating with nanosheet layers of the second type of semiconductor material;

forming bottom isolation regions over the second region of the substrate;

forming nanosheet source or drain (S/D) regions over the bottom isolation regions and adjacent end regions of the nanosheet layers of the first type of semiconductor material alternating with nanosheet layers of the second type of semiconductor material in the second region of the nanosheet stack;

replacing the nanosheet layers of the second type of semiconductor material in the second region of the nanosheet stack with a first set of conductive gate regions; and

forming a second conductive gate region over and around the second region of the nanosheet stack.

13. The method of claim 12 further comprising:

performing extended-gate (EG) fabrication operations to form a EG FET device in a third region of the substrate, wherein the EG fabrication operations include:

forming a fin in the third region of the substrate;

forming selected ones of the bottom isolation regions over the third region of the substrate and adjacent to a portion of the fin;

forming EG S/D regions over the selected ones of the bottom isolation regions and adjacent sidewalls of the fin; and

forming selected portions of the second conductive gate region over and around the fin.

14. A method of fabricating devices on a substrate, the method comprising:

performing memory fabrication operations to form a non-volatile memory device in a first region of the substrate, wherein the memory fabrication operations include:

forming a first region of the nanosheet stack over a first region of the substrate, wherein the first region of nanosheet stack comprises alternating layers of sacrificial nanosheets and non-sacrificial nanosheets;

replacing at least a portion of the first region of the nanosheet stack with a control gate; and

providing a charge trapping region of the non-volatile memory device under the control gate;

performing nanosheet fabrication operations to form a nanosheet field effect transistor (FET) device in a second region of the substrate, wherein the nanosheet fabrication operations include:

forming a second region of the nanosheet stack over a second region of the substrate, wherein the second region of the nanosheet stack comprises the alternating layers of sacrificial nanosheets and non-sacrificial nanosheets;

forming bottom isolation regions over the second region;

forming nanosheet source or drain (S/D) regions over the bottom isolation regions and adjacent end regions of the non-sacrificial nanosheets of the second region of the nanosheet stack;

replacing the sacrificial nanosheets of the second region of the nanosheet stack with a first set of conductive gate regions; and

forming a second conductive gate region over and around the second region of the nanosheet stack; and

performing extended-gate (EG) fabrication operations to form an EG FET device in a third region of the substrate, wherein the EG fabrication operations include:

forming a fin in the third region of the substrate;

forming selected ones of the bottom isolation regions over the third region of the substrate and adjacent to a portion of the fin;

forming EG S/D regions over the bottom isolation regions and adjacent sidewalls of the fin; and

forming selected portions of the second conductive gate region over and around the fin.

15. The method of claim 14 , wherein:

the memory fabrication operations further include forming memory source or drain (S/D) regions over the first region of the substrate;

a portion of the first region of the substrate is between a first one of the S/D regions and a second one of the S/D regions;

a channel region comprises the portion of the first region of the substrate that is between the first one of the S/D regions and the second one of the S/D regions;

the non-volatile memory device comprises a non-volatile memory transistor, the control gate, and the charge trapping region;

the non-volatile memory transistor comprises:

the first one of the S/D regions;

the second one of the S/D regions; and

the channel region; and

the charge trapping region comprises at least one of the nanosheet layers of the second region of the nanosheet stack.

16. The method of claim 14 , wherein:

the memory fabrication operations further include forming a dielectric stack under the control gate; and

the dielectric stack comprises the charge trapping region.

17. An integrated circuit structure comprising:

a first region of a nanosheet stack formed over a first region of a substrate, wherein the first region of the nanosheet stack comprises a nanosheet layer of a first type of semiconductor material and a nanosheet layer of a second type of semiconductor material;

a control gate formed over the first region of the nanosheet stack of the non-volatile memory device; and

a charge trapping region of the non-volatile memory device under the control gate, wherein the charge trapping region comprises the nanosheet layer of the first type of semiconductor material and the nanosheet layer of the second type of semiconductor material;

memory source or drain (S/D) regions over the first region of the substrate;

a portion of the first region of the substrate positioned between a first one of the S/D regions and a second one of the S/D regions; and

a channel region comprising the portion of the first region of the substrate that is positioned between the first one of the S/D regions and the second one of the S/D regions;

wherein a non-volatile memory device of the integrated circuit comprises a non-volatile memory transistor, the control gate, and the charge trapping region; and

wherein the non-volatile memory transistor comprises:

the first one of the S/D regions;

the second one of the S/D regions; and

the channel region.

18. The structure of claim 17 , wherein:

the first type of semiconductor material comprises silicon; and

the second type of semiconductor material comprises silicon germanium.

19. The structure of claim 17 further comprising:

a nanosheet field effect transistor (FET) device formed in a second region of the substrate, wherein the nanosheet FET device includes:

a second region of the nanosheet stack formed over a second region of the substrate, wherein the second region of the nanosheet stack comprises nanosheet layers of the first type of semiconductor material;

bottom isolation regions formed over the second region of the substrate;

nanosheet S/D regions over the bottom isolation regions and adjacent end regions of the nanosheet layers of the first type of semiconductor material in the second region of the nanosheet stack;

a first set of conductive gate regions formed in spaces between the nanosheet layers of the first type of semiconductor material in the second region of the nanosheet stack; and

a second conductive gate region over and around the second region of the nanosheet stack.

20. The structure of claim 19 further comprising:

an extended-gate (EG) FET device in a third region of the substrate, wherein the EG FET device includes:

a fin formed in the third region of the substrate;

selected ones of the bottom isolation regions formed over the third region of the substrate and adjacent to a portion of the fin;

EG S/D regions over the selected ones of the bottom isolation regions and adjacent sidewalls of the fin; and

selected portions of the second conductive gate region formed over and around the fin.