Nanosheet field-effect transistors including a two-dimensional semiconducting material
Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A plurality of channel layers are arranged in a layer stack, and a source/drain region is connected with the plurality of channel layers. A gate structure includes a plurality of sections that respectively surround the plurality of channel layers. The plurality of channel layers contain a two-dimensional semiconducting material.
1. A structure for a field-effect transistor, the structure comprising:
a plurality of channel layers arranged in a layer stack;
a source/drain region connected with the plurality of channel layers; and
a gate structure including a plurality of sections that respectively surround the plurality of channel layers,
wherein the plurality of channel layers are comprised of a two-dimensional semiconducting material, and the source/drain region is comprised of the two-dimensional semiconducting material.
2. The structure of claim 1 wherein the two-dimensional semiconducting material is a transition metal dichalcogenide.
3. The structure of claim 1 wherein the two-dimensional semiconducting material is molybdenum disulphide, hafnium disulfide, zirconium disulfide, tungsten disulfide, tin sulfide, or tungsten diselenide.
4. The structure of claim 1 wherein the two-dimensional semiconducting material is graphene.
5. The structure of claim 1 wherein the two-dimensional semiconducting material of the source/drain region contains a dopant effective to increase an electrical conductivity of the two-dimensional semiconducting material of the source/drain region.
6. The structure of claim 1 further comprising:
a contact coupled with the two-dimensional semiconducting material of the source/drain region.
7. The structure of claim 6 wherein the two-dimensional semiconducting material of the source/drain region contains a dopant effective to increase electrical conductivity.
8. The structure of claim 1 wherein each channel layer includes a first section and a second section that are separated by an air gap.
9. The structure of claim 1 wherein each channel layer includes a first section and a second section spaced from the first section, and the structure further comprising:
a dielectric layer arranged between the first section and the second section of each channel layer.
10. The structure of claim 1 wherein each channel layer has a thickness of one nanometer to three nanometers.
11. The structure of claim 1 wherein each channel layer is a sheet including a monolayer of atoms.
12. A method of forming a field-effect transistor, the method comprising:
forming a plurality of nanosheet channel layers arranged in a layer stack;
forming a gate structure including a plurality of sections that respectively surround the plurality of nanosheet channel layers;
after forming the gate structure, removing the plurality of nanosheet channel layers to form a plurality of spaces between the plurality of sections of the gate structure; and
depositing a two-dimensional semiconducting material in the plurality of spaces between the plurality of sections of the gate structure to form a plurality of replacement channel layers.
13. The method of claim 12 wherein the two-dimensional semiconducting material is a transition metal dichalcogenide.
14. The method of claim 12 wherein the two-dimensional semiconducting material is deposited as a conformal coating on a sidewall of the layer stack to provide a source/drain region that is connected with the plurality of replacement channel layers.
15. The method of claim 14 further comprising:
introducing a dopant by a plasma doping process into the two-dimensional semiconducting material of the source/drain region that is effective to increase an electrical conductivity of the two-dimensional semiconducting material of the source/drain region.
16. The method of claim 15 further comprising:
forming a contact coupled with the two-dimensional semiconducting material of the source/drain region.
17. The method of claim 12 wherein each space is partially filled by a first section and a second section of the two-dimensional semiconducting material, and an air gap is arranged in a portion of each space between the first section and the second section of the two-dimensional semiconducting material.
18. The method of claim 12 wherein each space is partially filled by a first section and a second section of the two-dimensional semiconducting material, and the method further comprises:
depositing a dielectric layer in a portion of each space that is arranged between the first section and the second section of the two-dimensional semiconducting material.
19. The method of claim 12 wherein each channel layer is a sheet including a monolayer of atoms.
20. The structure of claim 1 wherein the layer stack has a sidewall, and the two-dimensional semiconducting material of the source/drain region is arranged as a conformal coating on the sidewall of the layer stack.