Gate-all-around nanosheet-FET with variable channel geometries for performance optimization
A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W 1 and the first nanosheet is tapered in the X-direction to have a length L 1 . A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W 2 and the first nanosheet is tapered in the X-direction to have a length L 2 . Wherein the widths W 1 and W 2 are different from each other and the lengths L 1 and L 2 are different from each other and wherein the substrate includes a tapered surface in the Y-direction.
1. A semiconductor device comprising:
a first nanosheet having a tapered profile in the Y-direction to have a width W 1 and the first nanosheet is tapered in the X-direction to have a length L 1 , wherein the tapered profile in the Y-direction is at a first angle and the tapered profile in the X-direction is at a second angle;
a second nanosheet having a tapered fin profile in the Y-direction to have a width W 2 and the first nanosheet is tapered in the X-direction to have a length L 2 , wherein the tapered profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle, wherein the first angle and the second angle are different;
a bottom dielectric isolation layer located beneath the first and second nanosheets, wherein the bottom dielectric isolation layer has a tapered profile in the Y-direction and a different profile in the X-direction; and
wherein the widths W 1 and W 2 are different from each other and the lengths L 1 and L 2 are different from each other.
2. The semiconductor device of claim 1 , wherein the second nanosheet is located above the first nanosheet.
3. The semiconductor device of claim 2 , wherein the width W 1 >W 2 and the length L 1 >L 2 .
4. The semiconductor device of claim 3 , further comprising:
a nanowire located above the second nanosheet, wherein the nanowire has a tapered fin profile in the Y-direction and a tapered profile in the X-direction, wherein the nanowire has a width W 3 and a length L 3 , wherein the width W 1 >W 2 >W 3 and the length L 1 >L 2 >L 3 , wherein the tapered fin profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle.
5. The semiconductor device of claim 3 , further comprising:
a third nanosheet located above the second nanosheet, wherein the third nanosheet has a tapered fin profile in the Y-direction and a tapered profile in the X-direction, wherein the third nanosheet has a width W 3 and a length L 3 , wherein the width W 1 >W 2 >W 3 and the length L 1 >L 2 >L 3 , wherein the tapered fin profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle.
6. The semiconductor of claim 1 , wherein the outer edges of the first nanosheet and the second nanosheet are tapered at angle A 2 in the X-direction.
7. The semiconductor of claim 6 , further comprising:
a gate layer located between the first nanosheet and the second nanosheet; and
an inner spacer located adjacent to the gate layer, where the inner spacer is located between the first nanosheet and the second nanosheet.
8. The semiconductor of claim 7 , wherein the outer edge of the inner spacer is tapered at angle A 4 , wherein the A 4 is about equal to angle A 2 .
9. The semiconductor of claim 7 , wherein the outer edge of the gate layer is tapered at angle A 3 , wherein the angle A3 is about equal to angle A 2 .
10. A semiconductor device comprising:
a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width WI and the first nanosheet is tapered in the X-direction to have a length L 1 , wherein the tapered profile in the Y-direction is at a first angle and the tapered profile in the X-direction is at a second angle; and
a second nanosheet located on top of the first nanosheet, wherein the second nanosheet is tapered in the Y-direction to have a width W 2 and the second nanosheet is tapered in the X-direction to have a length L 2 , wherein the tapered profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle, wherein the first angle and the second angle are different;
a bottom dielectric isolation layer located beneath the first and second nanosheets, wherein the bottom dielectric isolation layer has a tapered profile in the Y-direction and a different profile in the X-direction;
wherein the widths W 1 and W 2 are different from each other and the lengths L 1 and L 2 are different from each other; and
wherein the substrate includes a tapered surface in the Y-direction.
11. The semiconductor device of claim 10 , wherein the width W 1 >W 2 and the length L 1 >L 2 .
12. The semiconductor device of claim 11 , further comprising:
a nanowire located above the second nanosheet, wherein the nanowire has a tapered fin profile in the Y-direction and a tapered profile in the X-direction, wherein the nanowire has a width W 3 and a length L 3 , wherein the width W 1 >W 2 >W 3 and the length L 1 >L 2 >L 3 , wherein the tapered fin profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle.
13. The semiconductor device of claim 11 , further comprising:
a third nanosheet located above the second nanosheet, wherein the third nanosheet has a tapered fin profile in the Y-direction and a tapered profile in the X-direction, wherein the third nanosheet has a width W 3 and a length L 3 , wherein the width W 1 >W 2 >W 3 and the length L 1 >L 2 >L 3 , wherein the tapered fin profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle.
14. The semiconductor of claim 10 , wherein the outer edges of the first nanosheet and the second nanosheet are tapered at angle A 2 in the X-direction.
15. The semiconductor of claim 14 , further comprising:
a gate layer located between the first nanosheet and the second nanosheet; and
an inner spacer located adjacent to the gate layer, where the inner spacer is located between the first nanosheet and the second nanosheet.
16. The semiconductor of claim 15 , wherein the outer edge of the inner spacer is tapered at angle A 4 , wherein the A 4 is about equal to angle A 2 .
17. The semiconductor of claim 15 , wherein the outer edge of the gate layer is tapered at angle A 3 , wherein the angle A3 is about equal to angle A 2 .
18. A method comprising:
forming a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W 1 and the first nanosheet is tapered in the X-direction to have a length L 1 , wherein the tapered profile in the Y-direction is at a first angle and the tapered profile in the X-direction is at a second angle, wherein the first nanosheet was tapered in the Y-direction during a first etching process, wherein the first nanosheet was tapered in the X-direction during a second etching process; and
forming a second nanosheet located on top of the first nanosheet, wherein the second nanosheet is tapered in the Y-direction to have a width W 2 and the second nanosheet is tapered in the X-direction to have a length L 2 , wherein the tapered profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle, wherein the first angle and the second angle are different, wherein the second nanosheet was tapered in the Y-direction during the first etching process, wherein the second nanosheet was tapered in the X-direction during the second etching process;
forming a bottom dielectric isolation layer located beneath the first and second nanosheets, wherein the bottom dielectric isolation layer has a tapered profile in the Y-direction and a different profile in the X-direction, wherein the bottom dielectric isolation layer was tapered in the Y-direction during the first etching process;
wherein the widths W 1 and W 2 are different from each other and the lengths L 1 and L 2 are different from each other; and wherein the substrate includes a tapered surface in the Y-direction.