Transistors with H-shaped or U-shaped channels and method for forming the same
A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.
1. A method comprising:
forming a fin structure having a first sidewall, and a second sidewall above a substrate, the fin structure including:
a first sacrificial semiconductor layer above the substrate,
a first silicon region on the first sacrificial semiconductor layer, and
a second sacrificial semiconductor layer on the first silicon region;
forming a shallow trench isolation (STI) above the substrate adjacent to the fin structure, wherein an uppermost surface of the STI is positioned below a bottommost extent of the first silicon region;
forming a second silicon region extending vertically along the first sidewall of the fin structure, the second silicon region contacting a first surface of the first silicon region;
forming a third silicon region extending vertically along the second sidewall of the fin structure, the third silicon region contacting a second surface the first silicon region;
forming a dummy gate structure on a first portion of the fin structure, the second silicon region and the third silicon region;
removing an exposed portion of the fin structure, the second silicon region and the third silicon region free from the dummy gate structure;
replacing a portion of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer positioned under the dummy gate structure with a spacer material layer;
forming a source/drain region from the first silicon region;
removing a remainder of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer; and
replacing a portion of the dummy gate structure with a replacement metal gate (RMG) body surrounding the first silicon region, the second silicon region and the third silicon region.
2. The method of claim 1 , wherein the dummy gate structure includes:
a dummy body having sidewalls, and
spacers on the sidewalls of the dummy body, and
wherein the portion of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer replaced by the spacer material layer is a portion of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer positioned under the spacers of the dummy gate structure.
3. The method of claim 2 , further comprising before removing the remainder of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer, removing the dummy body of the dummy gate structure and the STI.
4. The method of claim 1 , wherein the first sacrificial semiconductor layer and the second sacrificial semiconductor layer comprise silicon germanium (SiGe).
5. The method of claim 1 , wherein forming the STI includes allowing a portion of the first sacrificial semiconductor layer below the first silicon region to remain exposed, and wherein a cross-sectional geometry of the first silicon region, the second silicon region, and the third silicon region together is substantially H-shaped.
6. The method of claim 1 , wherein forming the STI includes forming the STI to cover the first sacrificial semiconductor layer below the first silicon region, and a cross-sectional geometry of the first silicon region, the second silicon region, and the third silicon region together is substantially U-shaped.
7. The method of claim 1 , wherein the forming the second silicon region includes epitaxially growing the first surface of the first silicon region at the first sidewall.
8. The method of claim 1 , wherein the forming the third silicon region includes epitaxially growing the second surface of the first silicon region at the second sidewall.
9. A method comprising:
forming a first isolation material layer on an uppermost surface of a substrate of the semiconductor structure;
forming a fin structure having a first sidewall, and a second sidewall on the first isolation material layer, the fin structure including:
a first sacrificial semiconductor layer on the first isolation material layer,
a first silicon region on the first sacrificial semiconductor layer,
a second sacrificial semiconductor layer on the first silicon region,
a second silicon region on the second sacrificial semiconductor layer, and
a third sacrificial semiconductor layer on the second silicon region;
forming a third silicon region extending vertically along the first sidewall of the fin structure, the third silicon region contacting a first surface of the first silicon region and the second silicon region at the first sidewall;
forming a fourth silicon region extending vertically along the second sidewall of the fin structure, the fourth silicon region contacting a second surface of the first silicon region and the second silicon region at the second sidewall;
forming an organic planarization layer (OPL) above the first isolation material layer and adjacent to the third silicon region and the fourth silicon region, wherein an upper surface of the OPL is positioned above an uppermost extent of the first silicon region;
forming spacers above the OPL and on the fin structure, the third silicon region, and the fourth silicon region, wherein a bottommost surface of the spacers is positioned on the upper surface of the OPL;
removing an upper portion of the OPL positioned below the spacers to expose a portion of the third silicon region and the fourth silicon region; and
removing a portion of the third silicon region and the fourth silicon region positioned between the first silicon region and the second silicon region to form a first, lower channel and a second, upper channel positioned, the second, upper channel positioned above the first, lower channel.
10. The method of claim 9 , wherein the first, lower channel and the second, upper channel include one of a substantially U-shaped cross-sectional geometry and a substantially H-shaped geometry.
11. The method of claim 9 , further comprising before forming the third silicon region and the fourth silicon region, forming a shallow trench isolation (STI) on the first isolation material layer adjacent to the fin structure, wherein an uppermost surface of the STI is positioned below a bottommost extent of the first silicon region.