Bottom channel isolation in nanosheet transistors

1. A method for forming a nanosheet semiconductor device, the method comprising:

forming a buffer layer comprising epitaxial silicon and germanium over a substrate, the buffer layer comprising a germanium concentration of about 10 atomic percent to about 30 atomic percent;

forming a nanosheet stack comprising alternating layers of silicon channel nanosheets and silicon germanium sacrificial nanosheets;

selectively removing the sacrificial nanosheets such that a space is formed between adjacent channel nanosheets and between a bottommost channel nanosheet in the nanosheet stack and the buffer layer;

forming a first dielectric layer in the space on the buffer layer and on a surface of the channel nanosheets, wherein forming the first dielectric layer in the space partially fills the space, and wherein the first dielectric layer comprises germanium oxide;

annealing the substrate and the first dielectric layer at a temperature of about 700° C. for about 30 seconds in an inert environment to form a modified buffer layer and a dielectric isolation layer on a surface of the modified buffer layer by reacting an uppermost portion of the buffer layer with the first dielectric layer, the modified buffer layer comprising an increased germanium concentration relative to the buffer layer, the modified buffer layer having a lower conductivity than each of the channel nanosheets, wherein the buffer layer is retained under the modified buffer layer, wherein the channel nanosheets and the first dielectric on the surface of the channel nanosheets are not reactive during the annealing, and wherein the dielectric isolation layer comprises silicon dioxide;

selectively removing the first dielectric layer from the surface of channel nanosheets; and

forming a high k dielectric material around the channel nanosheets and a gate material around the high k dielectric material, wherein the high k dielectric material is on an uppermost surface of the dielectric isolation layer, and the gate material is on the high k dielectric material.

2. The method of claim 1 , wherein annealing is performed in an inert gas environment.

3. The method of claim 1 , wherein annealing to form the modified buffer layer is according to reaction scheme:

Si+Ge+2GeO 2 →SiO 2 +Ge+GeO.

4. The method of claim 3 , wherein annealing to form the modified buffer layer comprises increasing a concentration of the germanium in the buffer layer.

5. The method of claim 3 , wherein reacting the buffer layer with the first dielectric layer comprises oxidizing silicon in the buffer layer to form the silicon dioxide in the dielectric isolation layer.

6. The method of claim 1 , wherein after annealing, a concentration of germanium in the buffer layer is increased such that the buffer layer comprises from about 15 atomic percent germanium to about 35 atomic percent germanium.

7. The method of claim 1 further comprising forming source and drain regions on the buffer layer, the nanosheet stack being between the source and drain regions.