IP Library Granted Patent US 10,777,556
Granted Patent B2
US 10,777,556 · App. 16/149,125 · Granted Sep 15, 2020

Semiconductor device and method for fabricating the same

Inventors: En-Chiuan Liou (Tainan, TW); Yu-Cheng Tung (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L27/0924H01L21/0217H01L21/02129H01L21/2256H01L21/823412H01L21/823418H01L21/823431H01L21/823437H01L21/823468H01L21/823807H01L21/823814H01L21/823821H01L21/823828H01L21/823864H01L27/0886H01L29/66803H01L21/823892
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Quick Facts
Patent No.
US 10,777,556
App. No.
16/149,125
Granted
Sep 15, 2020
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

Claims (13)

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of semiconductor fins; and

a first fin bump between the plurality of semiconductor fins, wherein the first fin bump comprises a first sidewall spacer, and wherein the first sidewall spacer comprises a solid-state dopant source layer and an insulating buffer layer.

2. The semiconductor device according to claim 1 , wherein the solid-state dopant source layer comprises a borosilicate glass (BSG) layer.

3. The semiconductor device according to claim 1 , wherein the solid-state dopant source layer comprises a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.

4. The semiconductor device according to claim 1 , wherein the insulating buffer layer comprises silicon nitride.

5. The semiconductor device according to claim 1 , wherein the insulating buffer layer is disposed on the solid-state dopant source layer.

6. The semiconductor device according to claim 1 further comprises a recessed region in the semiconductor substrate and next to the first fin bump.

7. The semiconductor device according to claim 6 , wherein the recessed region is filled with a dielectric layer.

8. The semiconductor device according to claim 7 further comprises a gate segment on the dielectric layer and a gate edge of the gate segment that is partially overlapped with the first fin bump.

9. The semiconductor device according to claim 1 , wherein the first sidewall spacer has a top surface that is higher than that of the first fin bump.

10. The semiconductor device according to claim 1 further comprises a second fin bump, wherein the second fin bump comprises a second sidewall spacer that has different structure from the first sidewall spacer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →