Generating timestamps on a packet-oriented bus

1. A method performed on a packet-oriented bus at a point between a source of a data packet and a destination of the data packet, the method comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a device connected to the packet-oriented bus; and

outputting the timestamp report to the device;

wherein detecting, determining, generating, and outputting are performed by digital logic connected to the packet-oriented bus; and

wherein detecting the format comprises detecting that the data packet is a write packet, the write packet for writing to one or more predefined addresses.

2. The method of claim 1 , wherein the device is a microprocessor; and

wherein the digital logic is located on a second device connected to the packet-oriented bus that is separate from the microprocessor.

3. The method of claim 2 , wherein the digital logic is connected to the packet-oriented bus between the microprocessor and a third device that outputs the data packet.

4. The method of claim 1 , wherein the device is a microprocessor; and

wherein receipt of the write packet triggers or produces an interrupt for the microprocessor.

5. A method performed on a packet-oriented bus at a point between a source of a data packet and a destination of the data packet, the method comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a first device connected to the packet-oriented bus; and

outputting the timestamp report to the device;

wherein detecting, determining, generating, and outputting are performed by digital logic connected to the packet-oriented bus;

wherein the first device is a microprocessor;

wherein the digital logic is located on a second device connected to the packet-oriented bus that is separate from the microprocessor;

wherein the digital logic is connected to the packet-oriented bus between the microprocessor and a third device that outputs the data packet;

wherein the packet-oriented bus is a peripheral component interconnect express (PCI Express) bus; and

wherein the third device interfaces to an IEEE 1394 bus, the IEEE bus being located on a path to a device under test.

6. A method performed on a packet-oriented bus at a point between a source of a data packet and a destination of the data packet, the method comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a device connected to the packet-oriented bus; and

outputting the timestamp report to the device;

wherein detecting, determining, generating, and outputting are performed by digital logic connected to the packet-oriented bus;

wherein the packet-oriented bus is a peripheral component interconnect express (PCI Express) bus; and

wherein the digital logic is located at a root complex of the PCI Express bus.

7. A method performed on a packet-oriented bus at a point between a source of a data packet and a destination of the data packet, the method comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a first device connected to the packet-oriented bus; and

outputting the timestamp report to the first device;

wherein detecting, determining, generating, and outputting are performed by digital logic connected to the packet-oriented bus;

wherein the data packet is output from a second device connected to the packet-oriented bus;

wherein the timestamp report is output to memory on the first device; and

wherein the timestamp report is used in testing operation a device under test in communication with the second device.

8. The method of claim 6 or 1 , wherein the device is a first device;

wherein the data packet is output from a second device connected to the packet-oriented bus to a third device connected to the packet-oriented bus, the digital logic being on a path of the packet-oriented bus between the second device and the third device.

9. The method of claim 8 , wherein the first device is a microprocessor.

10. The method of claim 5 , 6 , 1 , or 7 , wherein the time is determined by referencing a clock available on the packet-oriented bus.

11. The method of claim 5 , 6 , 1 , or 7 , wherein the timestamp report is output over the packet-oriented bus.

12. A system comprising:

a packet-oriented bus;

a first device connected to the packet-oriented bus for outputting a data packet over the packet-oriented bus; and

digital logic connected to the packet-oriented bus, the digital logic being configured to perform operations comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a second device; and

outputting the timestamp report to the second device over the packet-oriented bus;

wherein the digital logic is connected to the packet-oriented bus at a point between the first device and a destination of the data packet; and

wherein detecting the format comprises detecting that the data packet is a write packet, the write packet for writing to one or more predefined addresses.

13. The system of claim 12 , wherein the second device is a microprocessor; and

wherein the digital logic is located on a third device connected to the packet-oriented bus that is separate from the microprocessor.

14. The system of claim 13 , wherein the third device is connected to the packet-oriented bus between the microprocessor and the first device.

15. The system of claim 12 , wherein the second device is a microprocessor; and

wherein receipt of the write packet triggers or produces an interrupt for the microprocessor.

16. A system comprising:

a packet-oriented bus;

a first device connected to the packet-oriented bus for outputting a data packet over the packet-oriented bus; and

digital logic connected to the packet-oriented bus, the digital logic being configured to perform operations comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a second device; and

outputting the timestamp report to the second device over the packet-oriented bus;

wherein the digital logic is connected to the packet-oriented bus at a point between the first device and a destination of the data packet;

wherein the second device is a microprocessor;

wherein the digital logic is located on a third device connected to the packet-oriented bus that is separate from the microprocessor;

wherein the third device is connected to the packet-oriented bus between the microprocessor and the first device;

wherein the packet-oriented bus is a peripheral component interconnect express (PCI Express) bus; and

wherein the first device interfaces to an IEEE 1394 bus, the IEEE bus being located on a path to a device under test.

17. A system comprising:

a packet-oriented bus;

a first device connected to the packet-oriented bus for outputting a data packet over the packet-oriented bus; and

digital logic connected to the packet-oriented bus, the digital logic being configured to perform operations comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a second device; and

outputting the timestamp report to the second device over the packet-oriented bus;

wherein the digital logic is connected to the packet-oriented bus at a point between the first device and a destination of the data packet;

wherein the destination is the second device, the digital logic being on a path of the packet-oriented bus between the first device and the second device.

18. The system of claim 17 , wherein the second device is a microprocessor.

19. A system comprising:

a packet-oriented bus;

a first device connected to the packet-oriented bus for outputting a data packet over the packet-oriented bus; and

digital logic connected to the packet-oriented bus, the digital logic being configured to perform operations comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a second device; and

outputting the timestamp report to the second device over the packet-oriented bus;

wherein the digital logic is connected to the packet-oriented bus at a point between the first device and a destination of the data packet;

wherein the packet-oriented bus is a peripheral component interconnect express (PCI Express) bus; and

wherein the digital logic is located at a root complex of the PCI Express bus.

20. A system comprising:

a packet-oriented bus;

a first device connected to the packet-oriented bus for outputting a data packet over the packet-oriented bus; and

digital logic connected to the packet-oriented bus, the digital logic being configured to perform operations comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a second device; and

outputting the timestamp report to the second device over the packet-oriented bus;

wherein the digital logic is connected to the packet-oriented bus at a point between the first device and a destination of the data packet;

wherein the timestamp report is addressed to memory on the second device; and

wherein the system is part of a test instrument configured to use the timestamp report in testing operation of a device under test in communication with the first device.

21. The system of claim 16 , 17 , 19 , 12 , or 20 , wherein the time is determined by referencing a clock available on the packet-oriented bus.

22. Automatic test equipment comprising:

a device interface board for interfacing to a device under test;

a test head comprising one or more test instruments, at least one of the test instruments comprising:

a packet-oriented bus;

a first device connected to the packet-oriented bus for outputting a data packet over the packet-oriented bus; and

digital logic connected to the packet-oriented bus, the digital logic being configured to perform operations comprising:

detecting a format of the data packet on the packet-oriented bus;

determining a time at which the data packet was detected;

generating a timestamp report containing the time, the timestamp report being addressed to a second device; and

outputting the timestamp report to the second device over the packet-oriented bus;

wherein the digital logic is connected to the packet-oriented bus at a point between the first device and a destination of the data packet; and

a data bus that is different from the packet-oriented bus and that is on a path between the first device and the device interface board.