Handling pipeline submissions across many compute units
One embodiment provides for a general-purpose graphics processing unit comprising multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution, a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity, and a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.
1. A general-purpose graphics processing unit comprising:
multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution;
a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity; and
a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.
2. The general-purpose graphics processing unit as in claim 1 , wherein the multiple processing elements are to maintain per-thread execution state.
3. The general-purpose graphics processing unit as in claim 2 , wherein the multiple processing elements are to enable switching between execution contexts.
4. The general-purpose graphics processing unit as in claim 3 , wherein the multiple processing elements are to yield execution at per-thread granularity.
5. The general-purpose graphics processing unit as in claim 1 , wherein the scheduler is to schedule threads of the warp at sub-warp granularity.
6. The general-purpose graphics processing unit as in claim 5 , wherein multiple processing elements are to complete a first sub-warp of threads and execute a second sub-warp of threads after the first sub-warp of threads completes.
7. The general-purpose graphics processing unit as in claim 1 , additionally including a streaming multiprocessor, the streaming multiprocessor including the multiple processing elements and the scheduler.
8. The general-purpose graphics processing unit as in claim 7 , the streaming multiprocessor additionally including a dispatch unit, wherein the dispatch unit is to dispatch threads to the multiple processing elements.
9. The general-purpose graphics processing unit as in claim 8 , the streaming multiprocessor additionally including a register file to store independent thread state.
10. A method of managing thread execution on a general-purpose graphics processing unit, the method comprising:
scheduling a warp to multiple processing elements of the general-purpose graphics processing unit, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity; and
grouping active threads from the warp for execution on the multiple processing elements, the multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads executed by the multiple processing elements is maintained on-chip during execution.
11. The method as in claim 10 , additionally comprising maintaining per-thread execution state on the multiple processing elements.
12. The method as in claim 11 , additionally comprising switching between execution contexts on the multiple processing elements.
13. The method as in claim 12 , additionally comprising yielding execution at per-thread granularity on the multiple processing elements.
14. The method as in claim 11 , additionally comprising scheduling threads of the warp to multiple processing elements at sub-warp granularity, wherein the multiple processing elements are to complete a first sub-warp of threads and execute a second sub-warp of threads after the first sub-warp of threads completes.
15. A data processing system comprising:
a memory to store instructions for execution; and
a general-purpose graphics processing unit comprising:
multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution;
a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity; and
a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.
16. The data processing system as in claim 15 , wherein the multiple processing elements are to maintain per-thread execution state, enable switching between execution contexts, and yield execution at per-thread granularity.
17. The data processing system as in claim 15 , wherein the scheduler is to schedule threads of the warp at sub-warp granularity.
18. The data processing system as in claim 17 , wherein multiple processing elements are to complete a first sub-warp of threads and execute a second sub-warp of threads after the first sub-warp of threads completes.
19. The data processing system as in claim 15 , the general-purpose graphics processing unit additionally including a streaming multiprocessor, the streaming multiprocessor including the multiple processing elements and the scheduler.
20. The data processing system as in claim 19 , the streaming multiprocessor additionally including a dispatch unit to dispatch threads to the multiple processing elements and a register file to store independent thread state.