Semiconductor devices having nonlinear bitline structures
View Patent ↗Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two-adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.
1. A semiconductor device comprising:
a substrate including a field area delimiting an active area;
a word line crossing the active area; and
a bit line having a wave shape and including a first bending portion, a second bending portion, and a third bending portion between the first bending portion and the second bending portion, the third bending portion crossing the active area, the first bending portion and the second bending portion on the field area, the first bending portion and the second bending portion opposite with respect to the active area,
wherein the first bending portion includes a highest point of the wave shape and the second bending portion includes a lowest point of the wave shape.
2. The semiconductor device of claim 1 , wherein the first bending portion and the second bending portion are diagonally opposite with respect to the active area.
3. The semiconductor device of claim 2 , wherein the first bending portion and the second bending portion are parallel with respect to the active area.
4. The semiconductor device of claim 1 , further comprising another active area, wherein a first conductive pattern is on or near an end of the active area, and a second conductive pattern is on or near an end of the other active area.
5. The semiconductor device of claim 4 , further comprising a contact separating insulation layer between the first conductive pattern and the second conductive pattern.
6. The semiconductor device of claim 5 , further comprising another bit line, wherein a first bit line spacer on the bit line and a second bit line spacer on the other bit line.
7. The semiconductor device of claim 6 , wherein the first conductive pattern and the second conductive pattern are between the first bit line spacer and the second bit line spacer.
8. The semiconductor device of claim 1 , wherein the highest point of the wave shape and the lowest point of the wave shape are on the field area.
9. The semiconductor device of claim 1 , further comprising a direct contact disposed between the active area and the third bending portion.