Coordinating power transitions between a smart interconnect and heterogeneous components
Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.
1. An apparatus comprising:
a semiconductor interconnect substrate electrically coupled to one or more components mounted thereon, wherein the semiconductor interconnect substrate includes within it a logic to handle sequence and/or control of power functions for the one or more components, wherein the semiconductor interconnect substrate includes within it a microcontroller unit; and
an interface coupled to the semiconductor interconnect substrate, wherein the interface is operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode,
wherein the logic, to handle sequence and/or control of power functions for the one or more components, comprises: a power management unit; a power kernel and controller coupled to the power management unit, and a memory coupled to the power kernel and controller,
wherein the power kernel and controller are operable to sequence one or more reset signals to reset the microcontroller unit, and
wherein the semiconductor interconnect substrate includes within it a microelectromechanical system-based temperature compensated crystal oscillator coupled to the microcontroller unit.
2. The apparatus of claim 1 , comprising:
a controller coupled to the interface and operable to transmit the configuration command set to the interface.
3. The apparatus of claim 1 ,
wherein the configuration command set is a second configuration command set; and
wherein the interface is also operable to carry a first configuration command set to the one or more components in the power-up mode.
4. The apparatus of claim 1 ,
wherein the configuration command set encompasses one or more commands to establish a plurality of interface states for the one or more components.
5. The apparatus of claim 4 ,
wherein the configuration command set encompasses a triggering event to apply the plurality of interface states substantially simultaneously.
6. The apparatus of claim 1 ,
wherein the configuration command set encompasses a resistor disconnection command.
7. The apparatus of claim 1 , comprising:
a strapping pin coupled to the controller;
wherein the configuration command set is based upon a logical value of the strapping pin.
8. The apparatus of claim 1 ,
wherein the configuration command set comprises one of: a Serial Peripheral Interface (SPI) command, and an Inter-Integrated Circuit (I2C) command.
9. A method comprising:
placing a semiconductor interconnect substrate into a power-up mode, the semiconductor interconnect substrate being electrically coupled to one or more components mounted thereon, wherein the semiconductor interconnect substrate includes within it a logic to handle sequence and/or control of power functions for the one or more components, wherein the semiconductor interconnect substrate includes within it a microcontroller unit; and
applying a configuration command set to the one or more components in a normal operation mode subsequent to the power-up mode,
wherein the logic, to handle sequence and/or control of power functions for the one or more components, comprises: a power management unit; a power kernel and controller coupled to the power management unit, and a memory coupled to the power kernel and controller,
wherein the power kernel and controller are operable to sequence one or more reset signals to reset the microcontroller unit, and
wherein the semiconductor interconnect substrate includes within it a microelectromechanical system-based temperature compensated crystal oscillator coupled to the microcontroller unit.
10. The method of claim 9 ,
wherein a controller circuitry coupled to the one or more components applies the configuration command set to the one or more components.
11. The method of claim 9 ,
wherein a component mounted on the semiconductor interconnect substrate applies the configuration command set to the one or more components.
12. The method of claim 9 ,
wherein the configuration command set encompasses one or more commands to establish a plurality of interface states for the one or more components.
13. The method of claim 12 ,
wherein the configuration command set encompasses a triggering event to apply the plurality of interface states substantially simultaneously.
14. The method of claim 9 ,
wherein the configuration command set encompasses a resistor disconnection command.
15. The method of claim 9 , wherein the configuration command set is a second configuration command set, the method comprising:
applying a first configuration command set to the one or more components in the power-up mode.
16. The method of claim 9 ,
wherein the configuration command set includes a command to electrically disconnect a mounted component from the semiconductor interconnect substrate.
17. A system comprising a power source and component coupled to the power source, the component including:
a semiconductor interconnect substrate electrically coupled to one or more components mounted thereon, wherein the semiconductor interconnect substrate includes within it a logic to handle sequence and/or control of power functions for the one or more components, wherein the semiconductor interconnect substrate includes within it a microcontroller unit; and
an interface coupled to the semiconductor interconnect substrate, wherein the interface is operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode,
wherein the logic, to handle sequence and/or control of power functions for the one or more components, comprises: a power management unit; a power kernel and controller coupled to the power management unit, and a memory coupled to the power kernel and controller,
wherein the power kernel and controller are operable to sequence one or more reset signals to reset the microcontroller unit, and
wherein the semiconductor interconnect substrate includes within it a microelectromechanical system-based temperature compensated crystal oscillator coupled to the microcontroller unit.
18. The system of claim 17 , comprising:
a controller coupled to the interface and operable to transmit the configuration command set to the interface.
19. The system of claim 17 ,
wherein the configuration command set encompasses at least one of: one or more commands to establish a plurality of interface states for the one or more components, a triggering event to apply a plurality of interface states substantially simultaneously, and a resistor disconnection command.
20. The system of claim 17 , comprising:
a strapping pin coupled to the controller;
wherein the configuration command set is based upon a logical value of the strapping pin.
21. The apparatus of claim 1 , wherein the power kernel and controller is operable to download system and/or component configuration from the memory.
22. The apparatus of claim 1 , wherein the interface is a first interface, and wherein the logic inside the semiconductor interconnect substrate is coupled to the microcontroller unit via a second interface.