Memory layout for reduced line loading
View Patent ↗Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.
1. A memory device comprising:
an array of bit cells comprising a plurality of rows and a plurality of columns, wherein the plurality of columns comprises a first column and a second column;
a first conductive line extending along the first column, wherein the first conductive line is electrically coupled to bit cells of the array in the first column;
a second conductive line extending along the second column, wherein the second conductive line is electrically coupled to bit cells of the array in the second column; and
a plurality of conductive bridges extending from the first conductive line to the second conductive line and electrically coupling the first and second conductive lines together.
2. The memory device according to claim 1 , wherein the plurality of columns further comprises a third column and a fourth column,
wherein the first conductive line extends along the third column and is electrically coupled to bit cells of the array in the third column, and
wherein the second conductive line extends along the fourth column and is electrically coupled to bit cells of the array in the fourth column.
3. The memory device according to claim 1 , wherein the conductive bridges are evenly spaced along the first column.
4. The memory device according to claim 1 , wherein the conductive bridges are line shaped and extend transverse to the first and second conductive lines in parallel.
5. The memory device according to claim 1 , wherein the plurality of conductive bridges comprises a first conductive bridge and a second conductive bridge, and
wherein the first and second conductive bridges border and are separated along the first column by two rows of the array.
6. The memory device according to claim 1 , wherein the plurality of columns further comprises a third column,
wherein the memory device further comprises a third conductive line that extends along the third column and is electrically coupled to bit cells of the array in the third column, and
wherein the conductive bridges extend from the first column to the second column and from the second column to the third column.
7. The memory device according to claim 1 , wherein the plurality of columns further comprises a third column,
wherein the conductive bridges extend between the first and second conductive lines, beginning and ending respectively at the first and second conductive lines;
wherein the memory device further comprises:
a third conductive line that extends along the third column and is electrically coupled to bit cells of the array in the third column; and
a plurality of second conductive bridges extending between the second and third conductive lines, beginning and ending respectively at the second and third conductive lines, wherein the conductive bridges and the second conductive bridges are spaced from each other and alternate along the second conductive line.
8. The memory device according to claim 1 , wherein the bit cells of the array are two-transistor one-resistor (2T1R) random-access memory (RRAM) cells.
9. The memory device according to claim 1 , wherein the bit cells of the array are one-transistor one-resistor (1T1R) random-access memory (RRAM) cells.
10. A memory device comprising:
an array of bit cells, wherein the array comprises a plurality of rows and a plurality of columns, and wherein the plurality of columns comprises a first pair of neighboring columns and a second pair of neighboring columns; and
a conductive structure electrically coupled to bit cells of the array in the first and second pairs of neighboring columns, wherein the conductive structure has a ladder-shaped top layout in which legs of the ladder-shaped top layout are elongated respectively along the first and second pairs of neighboring columns.
11. The memory device according to claim 10 , wherein the bit cells of the array comprise individual access transistors, and
wherein the conductive structure electrically couples to first source/drain regions of access transistors in each column of the first and second pairs of neighboring columns.
12. The memory device according to claim 11 , wherein the bit cells of the array comprise individual memory structures, and
wherein the memory structures respectively overlie and electrically couple to second source/drain regions of the access transistors.
13. The memory device according to claim 10 , wherein rungs of the ladder-shaped top layout have a two-row pitch and are elongated transverse to the columns of the array.
14. The memory device according to claim 10 , wherein the plurality of columns comprises a third pair of neighboring columns, and wherein the first and second pairs of neighboring columns are separated by the third pair of neighboring columns.
15. A memory device comprising:
an array of bit cells comprising a plurality of rows and a plurality of columns, wherein the plurality of columns comprises a first column and a second column;
a first bit line and a first source line extending along the first column, wherein bit cells of the array in the first column are electrically coupled to the first bit line and to the first source line;
a second bit line and a second source line extending along the second column, wherein bit cells of the array in the second column are electrically coupled to the second bit line and to the second source line; and
a conductive bridge electrically coupling the first and second source lines together.
16. The memory device according to claim 15 , wherein the plurality of columns further comprises a third column, and wherein the memory device further comprises:
a third bit line extending along the third column, wherein bit cells of the array in the third column are electrically coupled from the third bit line to the first source line.
17. The memory device according to claim 15 , wherein the conductive bridge repeats periodically along the first and second columns.
18. The memory device according to claim 15 , wherein the bit cells comprise individual access transistors, and wherein the memory device further comprises:
a plurality of word lines extending laterally and respectively along the rows, wherein the word lines electrically couple respectively to gates of the access transistors.
19. The memory device according to claim 15 , further comprising:
a substrate underlying the array, wherein the first and second source lines and the conductive bridge are at a common elevation above the substrate.
20. The memory device according to claim 15 , further comprising:
a third source line between the first and second source lines and electrically separated from the first and second source lines.