IP Library Granted Patent US 11,010,062
Granted Patent B2
US 11,010,062 · App. 16/160,008 · Granted May 18, 2021

Method for providing read data flow control or error reporting using a read data strobe

Inventors: Mark Alan McClain (San Diego, CA); Qamrul Hasan (Santa Clara, CA); Clifford Alan Zitlaw (San Jose, CA)
Assignee: Cypress Semiconductor Corporation
G06F3/0614G06F3/0653G06F3/0659G06F3/0665G06F3/0673G06F11/0745G06F11/0757G06F11/0769G06F11/0772
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Quick Facts
Patent No.
US 11,010,062
App. No.
16/160,008
Granted
May 18, 2021
Kind
B2
Abstract

A peripheral device includes a function block to provide data in response to a request from a host device, a data channel coupled with the function block to transmit the data from the function block to a host device as one or more packets, and output logic coupled with the data channel and configured to indicate validity of the data transmitted via the data channel by causing a signal to transition for each of the one or more packets of the data transmitted to the host device via the data channel, and transmit the signal to the host device.

Claims (67)

1. A peripheral device, comprising:

a function block configured to provide data in response to a request from a host device;

a data channel coupled with the function block and configured to transmit the data from the function block to the host device as one or more packets; and

output logic coupled with the data channel and configured to:

indicate validity of the data transmitted via the data channel by causing a signal comprising a read data strobe signal to transition for each of the one or more packets of the data transmitted to the host device via the data channel, and

transmit the signal to the host device, wherein the output logic further comprises a latency control circuit configured to, in response to the request, indicate the validity of the data prior to lapse of a maximum latency count.

2. The peripheral device of claim 1 , wherein:

the signal comprises a read data strobe signal; and

the output logic further comprises a latency control circuit configured to cause the signal to transition for each of the one or more packets by alternating the signal between an asserted state and a deasserted state.

3. The peripheral device of claim 1 , wherein:

the signal comprises an error detection signal; and

the output logic further comprises an error detection circuit configured to, after receiving the request from the host device, prevent transitioning of the signal for a duration exceeding a first maximum latency count in response to an error caused by the request.

4. The peripheral device of claim 1 , wherein:

the signal comprises an error detection signal;

the data channel is configured to, prior to lapsing of a first maximum latency count, transmit the data from the function block to the host device in response to the request from the host device; and

the output logic further comprises an error detection circuit configured to indicate an error while transmitting the data to the host device via the data channel by preventing transitioning of the signal for a duration exceeding a second maximum latency count.

5. A method, comprising:

providing data from a function block in response to a request from a host device;

transmitting the data from the function block to the host device as one or more packets via a data channel;

indicating validity of the data transmitted via the data channel by causing a signal to transition for each of the one or more packets of the data transmitted to the host device via the data channel;

indicating, in response to the request, the validity of the data prior to lapse of a maximum latency count, wherein the signal comprises a read data strobe signal; and

transmitting the signal to the host device.

6. The method of claim 5 , further comprising:

for each of the one or more packets, causing the signal to transition by alternating the signal between an asserted state and a deasserted state, wherein the signal comprises a read data strobe signal.

7. The method of claim 5 , further comprising:

after receiving the request from the host device, preventing transitioning of the signal for a duration exceeding a first maximum latency count in response to an error caused by the request.

8. The method of claim 5 , wherein:

transmitting the data from the function block to the host device is performed in response to the request from the host device and occurs prior to lapsing of a first maximum latency count; and

the method further comprises indicating an error while transmitting the data to the host device via the data channel by preventing transitioning of the signal for a duration exceeding a second maximum latency count.

9. The method of claim 5 , further comprising:

receiving the signal at an interface of the host device;

capturing the data from the one or more packets based on the transitions of the signal;

generating a count value by counting a plurality of clock cycles after a first transition of the signal; and

detecting an error based on determining that the count value exceeds a maximum latency count.

10. The method of claim 9 , further comprising counting the plurality of clock cycles by:

resetting the count value after the request is transmitted from the host device, and

incrementing the count value for each of a plurality of clock cycles detected after resetting the count value and prior to a transition of the signal.

11. A system, comprising:

a host device configured to transmit a request for data; and

a peripheral device comprising:

a function block configured to provide the data in response to receiving the request from the host device,

a data channel coupled with the function block and configured to transmit the data from the function block to the host device as one or more packets, and

output logic coupled with the data channel and configured to:

indicate validity of the data transmitted via the data channel by causing a signal comprising a read data strobe signal to transition for each of the one or more packets of the data transmitted to the host device via the data channel, and

transmit the signal to the host device, wherein the output logic further comprises a latency control circuit configured to, in response to the request, indicate the validity of the data prior to lapse of a maximum latency count.

12. The system of claim 11 , wherein:

the signal comprises a read data strobe signal; and

the output logic further comprises a latency control circuit configured to cause the signal to transition for each of the one or more packets by alternating the signal between an asserted state and a deasserted state.

13. The system of claim 11 , wherein:

the output logic further comprises an error detection circuit configured to, after receiving the request from the host device, prevent transitioning of the signal for a duration exceeding a first maximum latency count in response to an error caused by the request.

14. The system of claim 11 , wherein:

the data channel is configured to, prior to lapsing of a first maximum latency count, transmit the data from the function block to the host device in response to the request from the host device; and

the output logic further comprises an error detection circuit configured to indicate an error while transmitting the data to the host device via the data channel by preventing transitioning of the signal for a duration exceeding a second maximum latency count.

15. The system of claim 11 , wherein:

the host device is further configured to:

receive the signal at an interface of the host device, and

capture the data from the one or more packets based on the transitions of the signal, wherein the signal comprises a read data strobe signal; and

the host device further comprises a maximum latency error detection circuit configured to:

generate a count value by counting a plurality of clock cycles after a first transition of the signal, and

detect an error when the count value exceeds a first maximum latency count.

16. The system of claim 15 , wherein the maximum latency error detection circuit is configured to count the plurality of clock cycles by:

resetting the count value after the request is transmitted from the host device, and

incrementing the count value for each of a plurality of clock cycles detected after resetting the count value and prior to a transition of the signal.

17. The system of claim 15 , wherein the maximum latency error detection circuit is further configured to:

reset the count value in response to a first transition of the signal occurring prior to lapse of the first maximum latency count;

after resetting the count value, increment the count value for each of a plurality of clock cycles detected prior to a second transition of the signal; and

detect an error when the count value exceeds a second maximum latency count.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
SECURITY INTEREST Recorded Jul 31, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MUFG UNION BANK, N.A.
Reel/Frame 049917/0093 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2018
From: MCCLAIN, MARK ALAN; HASAN, QAMRUL; ZITLAW, CLIFFORD ALAN
To: SPANSION LLC
Reel/Frame 047374/0258 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2018
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 047377/0783 →
Continuity (3)
Continuation 15271527 · Sep 21, 2016
Continuation 14054265 · Oct 15, 2013
Related Publication 20190212920A1 · Jul 11, 2019